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| Preliminary Information AMD-762TM System Controller Software/BIOS Design Guide Publication # 24462 Rev: D Issue Date: March 2002 Preliminary Information (c) 2001, 2002 Advanced Micro Devices, Inc. All rights reserved. The contents of this document are provided in connection with Advanced Micro Devices, Inc. ("AMD") products. AMD makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specifications and product descriptions at any time without notice. No license, whether express, implied, arising by estoppel or otherwise, to any intellectual property rights is granted by this publication. Except as set forth in AMD's Standard Terms and Conditions of Sale, AMD assumes no liability whatsoever, and disclaims any express or implied warranty, relating to its products including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or infringement of any intellectual property right. AMD's products are not designed, intended, authorized or warranted for use as components in systems intended for surgical implant into the body, or in other applications intended to support or sustain life, or in any other application in which the failure of AMD's product could create a situation where personal injury, death, or severe property or environmental damage may occur. AMD reserves the right to discontinue or make changes to its products at any time without notice. Trademarks AMD, the AMD logo, AMD Athlon, and combinations thereof, AMD-751, AMD-760, AMD-761, AMD-762, AMD-766, AMD-768, and AMD PowerNow! are trademarks of Advanced Micro Devices, Inc. Other product names used in this publication are for identification purposes only and may be trademarks of their respective companies. Preliminary Information 24462D--March 2002 AMD-762TM System Controller Software/BIOS Design Guide Contents Revision History 1 Overview 1.1 xi 1 General BIOS Initialization Requirements . . . . . . . . . . . . . . . 2 1.1.1 1.1.2 1.1.3 1.1.4 1.1.5 AMD-762TM System Controller Configuration Spaces . . Special Configuration Sequencing Requirements . . . . Power-On Reset Initialization . . . . . . . . . . . . . . . . . . . . . Programming Reserved Bits . . . . . . . . . . . . . . . . . . . . . . Power Management Considerations . . . . . . . . . . . . . . . . 2 2 4 7 7 1.2 Recommended AMD AthlonTM Processor SYS_CONFIG Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2 AMD-762TM System Controller Programmer's Interface 2.1 2.2 9 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.2.1 Special Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.2.2 IACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.2.3 PCI Configuration Accesses . . . . . . . . . . . . . . . . . . . . . 15 2.3 Address Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.3.1 Socket2000 Address Decoding . . . . . . . . . . . . . . . . . . . 16 2.3.2 PCI/AGP Master Address Decoding . . . . . . . . . . . . . . . 17 2.4 Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 I/O Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Configuration Register Access . . . . . . . . . . . . . . . . . . . 26 Device 0: PCI Configuration Registers . . . . . . . . . . . . . 27 Device 0, Function 1: DDR PDL Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 2.4.5 Device 1: PCI-to-PCI Bridge Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 2.4.1 2.4.2 2.4.3 2.4.4 Table of Contents iii Preliminary Information AMD-762TM System Controller Software/BIOS Design Guide 24462D--March 2002 2.5 Memory-Mapped Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 147 2.5.1 AMD-762 System Controller GART Cache Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 2.5.2 Memory-Mapped Register Map . . . . . . . . . . . . . . . . . . 149 3 DDR SDRAM Interface 3.1 3.2 159 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 DDR DIMMS and DDR SDRAMs . . . . . . . . . . . . . . . . . . . . . 160 3.2.1 DDR Speed Grades . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 3.2.2 DDR DIMM Data from Serial Presence Detect (SPD) Device . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 3.3 3.4 Memory Space Configuration . . . . . . . . . . . . . . . . . . . . . . . . 162 DDR Memory DIMM Timings . . . . . . . . . . . . . . . . . . . . . . . . 167 3.4.1 Memory Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 3.5 3.6 3.7 Additional Memory Controller Settings . . . . . . . . . . . . . . . 171 DRAM Mode/Status Settings . . . . . . . . . . . . . . . . . . . . . . . . 174 ECC and Memory Scrubbing . . . . . . . . . . . . . . . . . . . . . . . . . 178 3.7.1 ECC and Memory Scrubbing Configuration . . . . . . . 181 3.8 Programmable Delay Lines (PDL) . . . . . . . . . . . . . . . . . . . . 183 3.8.1 Manual PDL Window Detection . . . . . . . . . . . . . . . . . 189 3.9 DDR I/O Drive Strength . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 4 Power Management 4.1 4.2 4.3 193 STPCLK# and Stop Grant . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 S1 Power-On Suspend State Requirements . . . . . . . . . . . . . 196 S3 Suspend to RAM State Requirements . . . . . . . . . . . . . . 197 4.3.1 STR Bit Control for S3 Support . . . . . . . . . . . . . . . . . . 198 4.4 4.5 iv Clock Throttling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 DDR DRAM Clock Enables . . . . . . . . . . . . . . . . . . . . . . . . . . 201 Table of Contents Preliminary Information 24462D--March 2002 AMD-762TM System Controller Software/BIOS Design Guide 5 PCI Bus Interface 5.1 5.2 203 66-MHz Primary Bus Option . . . . . . . . . . . . . . . . . . . . . . . . . 203 Delayed Transactions and Ordering Rules Usage . . . . . . . 204 5.2.1 Delayed Transactions and Target Latency . . . . . . . . 204 5.2.2 Transaction Ordering Rules . . . . . . . . . . . . . . . . . . . . 207 5.2.3 Special Arbitration Considerations for the Southbridge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 5.3 PCI Performance Optimization Options . . . . . . . . . . . . . . . . 210 5.3.1 Read Prefetching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 5.3.2 PCI Chaining . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 5.3.3 PCI Bus Parking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 6 AGP Interface 6.1 213 AGP Dynamic Compensation Requirements . . . . . . . . . . . . 213 6.1.1 The AGP 4X Dynamic Compensation Register . . . . . 214 6.1.2 Selection of 1.5- or 3.3-V AGP Signalling . . . . . . . . . . 215 6.2 6.3 6.4 Feature Override Bits for AGP Cards . . . . . . . . . . . . . . . . . 216 BIOS Initialization Requirements . . . . . . . . . . . . . . . . . . . . 217 AGP Miniport Driver Requirements . . . . . . . . . . . . . . . . . . 218 7 Recommended BIOS Settings 7.1 PCI Bus 0, Device 0, Function 0 Registers 219 . . . . . . . . . . . . . 220 7.1.1 Example Settings for Memory Timing . . . . . . . . . . . . 228 7.1.2 Examples: AGP Compensation Register Settings (0xB4-0xBB) . . . . . . . . . . . . . . . . . . . . . . . . . . 243 7.1.3 PCI Bus 0, Device 0, Function 1 Registers . . . . . . . . . 247 7.2 PCI Bus 0, Device 1, Function 0 Registers . . . . . . . . . . . . . 257 Table of Contents v Preliminary Information AMD-762TM System Controller Software/BIOS Design Guide 24462D--March 2002 vi Table of Contents Preliminary Information 24462D--March 2002 AMD-762TM System Controller Software/BIOS Design Guide List of Figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. AMD Athlon Processor Family Address Mapping . . . . . . . . . . 9 AMD Athlon Processor Family x86 Processor Address Mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 AMD-762 System Controller Logical Bus Hierarchy . . . . . . . 19 Two-Level GART Indexing . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 Suspend to RAM (STR_Control) Bits Usage. . . . . . . . . . . . . 200 Example of System with Flag and Data Stored across PCI Bus Domain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 List of Figures vii Preliminary Information AMD-762TM System Controller Software/BIOS Design Guide 24462D--March 2002 viii List of Figures Preliminary Information 24462D--March 2002 AMD-762TM System Controller Software/BIOS Design Guide List of Tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. AMD-762 System Controller Configuration Register Bits Unknown at RESET# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Recommended Settings for AMD Athlon Processor SYSCFG Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 AMD-762 System Controller Socket2000 Memory Map . . . . . . 10 AMD Athlon Processor Special Cycle Encodings . . . . . . . . . . . 12 I/O Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Device 0, Function 0 Configuration Register Map . . . . . . . . . . 27 AMD-762 System Controller SERR# Assertion Control and Status Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Wait State Settings for DRAM Timing Register . . . . . . . . . . . . 57 I/O Pad Drive Strength and Input Type . . . . . . . . . . . . . . . . . . . 99 DDR Memory Base Address Register Locations . . . . . . . . . . . 104 AMD-762 System Controller DRAM Addressing Modes . . . . 105 Device 0, Function 1 Configuration Register Map . . . . . . . . . 106 PDL Calibration Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 DDR PDL Configuration Register Locations. . . . . . . . . . . . . . 110 Device 1 Configuration Register Map . . . . . . . . . . . . . . . . . . . 126 AMD-762 System Controller Memory-Mapped Registers . . . 149 Typical CL Parameter Settings for PC1600 and PC2100 . . . . 161 DIMM Bank Address Bit Definition. . . . . . . . . . . . . . . . . . . . . 162 Memory Size Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 Total Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 AMD-762 System Controller DDR SDRAM Addressing Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 Memory Sizing Example, 128 Mbytes Total . . . . . . . . . . . . . . 166 Memory Sizing Example, 320 Mbytes Total . . . . . . . . . . . . . . 167 CAS Latency Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 DDR Device Timing Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 Dev 0:F0:0x54 Bit Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 System Related Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 Refresh Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 List of Tables ix Preliminary Information AMD-762TM System Controller Software/BIOS Design Guide 24462D--March 2002 Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. AMD-762 System Controller ECC Behavior (with ECC Enabled) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 Default DQS Delay versus System Clock Frequency . . . . . . . 185 AMD-762 System Controller Power Management Features for ACPI Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 AMD-762 Processor System Controller PCI Read Transaction Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 Allowable AGP Rate versus Signalling Level . . . . . . . . . . . . . 215 AGP I/O Settings for 1.5- and 3.3-V Signalling . . . . . . . . . . . . 218 x List of Tables Preliminary Information 24462D--March 2002 AMD-762TM System Controller Software/BIOS Design Guide Revision History Date Rev Description March/2002 D Fill in missing information for bits 28-30 in "BIU0 Status/Control" on page 63. Fill in missing information for bits 28-30 in "Bit Definitions BIU0 Status/Control (Dev0:F0:0x60)" on page 64. Fill in missing information for bits 28-30 in "BIU1 Status/Control" on page 68. Fill in missing information for bits 28-30 in "Bit Definitions BIU1 Status/Control (Dev0:F0:0x68)" on page 69. Remove erroneous characters in bit 18 of "PCI Arbitration Control" on page 78 (now properly reads Reserved.) In several cross references in text correct the page number given for Section 7. Added AMD-768 peripheral bus controller references throughout as the Southbridge device for the MPX chipset. Text added in the following locations explaining that the registers must be saved and restored when entering and exiting the S3 state : Section 1.1.5 on page 7, 2nd paragraph added Section 4 on page 193, first Note expanded Section 4.3 on page 197, paragraph two added Section 7 on page 219, paragraph added directly before section 7.1 Values for PSlewXfer and NSlewXfer changed from 01 and 00, respectively, to 11 and 11 in Table 34, "AGP I/O Settings for 1.5- and 3.3-V Signalling," on page 218. Initial full version release. Initial NDA release (programmer's interface section only). Dec./2001 C June/2001 Nov./2000 B A Revision History xi Preliminary Information AMD-762TM System Controller Software/BIOS Design Guide 24462D--March 2002 xii Revision History Preliminary Information 24462D--March 2002 AMD-762TM System Controller Software/BIOS Design Guide 1 Overview The AMD AthlonTM processor powers the next generation in computing platforms, delivering the ultimate performance for cutting-edge applications and an unprecedented computing experience. Th e A M D -7 62 TM s y st e m c o n t rol le r p rov ide s st a n d a rd Northbridge functionality for desktop personal computers u s i n g t h e A M D A t h l o n TM f a m i ly o f p ro c e s s o r s . Th i s functionality includes the processor interface as well as PCI, AGP, and main memory interface implementing state of the art Double Data Rate (DDR) synchronous DRAM technology. This document provides information typically required for development of the system BIOS and device drivers to properly program the AMD-762 system controller configuration registers. The document is organized as follows: Section 1 provides an overview of the general BIOS requirements for initializing the AMD-762 system controller configuration registers. Section 2 on page 9 contains a description of all AMD-762 system controller configuration registers. Section 3 on page 159 contains additional information on setup of the DDR SDRAM interface configuration registers. Section 4 on page 193 contains additional information on configuration of the power management features of the AMD-762 system controller. Section 5 on page 203 contains additional information on setup of the PCI bus interface configuration registers. Section 6 on page 213 contains additional information on setup of the AGP interface configuration registers. Section 7 on page 219 contains a list of recommended settings for many of the AMD-762 system controller configuration registers. Chapter 1 Overview 1 Preliminary Information AMD-762TM System Controller Software/BIOS Design Guide 24462D--March 2002 1.1 General BIOS Initialization Requirements The following sections provide general requirements for BIOS w h e n p r o g ra m m i n g t h e A M D -7 6 2 s y s t e m c o n t ro l l e r configuration registers. Note that the register descriptions also include some specific programming notes. 1.1.1 AMD-762TM System Controller Configuration Spaces The AMD-762 system controller contains both I/O and memorymapped configuration spaces as listed below. I/O Mapped Space * PCI configuration space address and data (CF8h, CFCh) * Host bridge registers mapped in PCI configuration space, device 0, function 0 * DDR interface PDL and I/O controls mapped in PCI configuration space to device 0, function 1 * PCI to PCI bridge/AGP registers mapped in PCI configuration space to device 1, function 0 GART Memory-Mapped Registers * Mapped in memory space as defined by the programming of Base Address 1: GART Memory Mapped Register Base 1.1.2 Special Configuration Sequencing Requirements This section outlines a few cases in the AMD-762 system controller configuration registers that require special handling for proper BIOS programming. Configuration Cycles Enable The AMD-762 system controller supports configuration address space as defined by the PCI Local Bus Specification, Revision 2.2, which defines a unique 256-byte space that is accessed through two 32-bit index registers mapped in I/O space. As defined in the PCI specification, configuration cycles are generated on the PCI bus only when bit 31 of the Configuration Address register is set. 2 Overview Chapter 1 Preliminary Information 24462D--March 2002 AMD-762TM System Controller Software/BIOS Design Guide Function 1 Space The configuration registers that control the memory interface's Programmable Delay Lines (PDLs) and I/O drive strengths are mapped to device 0: function 1 in the host bridge. This configuration space is disabled by default and requires a write to the PCI Control register's Func1_En (Dev 0:F0:0x4C, bit 0). The intent of this separate configuration space is that it is configured at initial power-on, subsequently disabled, and essentially protected from further writes. Note that the AMD-762 system controller does not report as a multifunction device (bit 7 is not set in the Header_Type field in the PCI Latency Timer and Header Type register in Dev 0:F0:0x0C). Reads to the PCI header that normally occupies offsets 00h- 3Fh return all 1s--that is, the normal PCI header registers are not implemented. Memory-Mapped BARs Five DWORD registers are accessed by the AMD-762 system controller AGP miniport driver as memory-mapped space. This space is defined by the Base Address 1: GART MemoryMapped Register Base (Dev 0:F0:0x14), which provides address bits [31:12] of the memory-mapped space. Note that this space is defined as a 4-Kbyte region, hence the lower address bits [11:4] are 0s. This register must be properly programmed by BIOS to allow the driver to access the memory-mapped space. Memory Holes Legacy memory holes are decoded in the normal region of main memory from 640 Kbyte to 1 Mbyte. The AMD-762 system controller does not allow PCI masters to access DRAM in this region unless the EV6_Mode bit is set in the PCI Arbitration Control Register. See "Bit Definitions PCI Arbitration Control (Dev0:F0:0x84)" on page 79. The AGP Status register (Dev 0:F0:0xA4) reports the AMD-762 system controller's capability to support AGP fast writes and the AGP-4X rate. The operating system normally reads these bits along with the same bits in the AGP card's status register, and uses this information to configure the AGP Command register (Dev 0:F0:0xA8) in the AMD-762 system controller and the AGP card. AGP Override Bits for 4X Rate and Fast Writes Chapter 1 Overview 3 Preliminary Information AMD-762TM System Controller Software/BIOS Design Guide 24462D--March 2002 The AMD-762 system controller provides BIOS the ability to override the reporting of fast write and 4X rate support. This override function is accomplished through a write to a separate register, which is required because the AGP Status register is specified as read-only in the AGP specification. R e f e r t o S e c t i o n 6 . 2 o n p a g e 2 1 6 fo r d e t a i l s o f t h i s implementation. Interrupt Pin Control R/W Attributes The Int_Pin field in the AGP/PCI Interrupt and Bridge Control register (Dev 1:F0:0x3C) is read-only by default and initializes to all 0s. If the BIOS is required to initialize this field to another value, it must first change this field to R/W by setting the Int_Pin_Cntl bit in the Miscellaneous Device 1 Control register (Dev 1:F0:0x40). The AMD-762 system controller does not use the Int_Pin field internally, the register is provided for software compatibility only. Silicon Revisions The reader is advised to read the AMD-762TM System Controller Revision Guide, order# 24089, for the most current information for the version of silicon being used. The silicon revision is available by reading the PCI revision ID and Class Code register in Dev 0:F0:0x08. 1.1.3 Power-On Reset Initialization All of the AMD-762 system controller's configuration registers must be initialized by BIOS after initial power-on, paying especially close attention to the registers that are not initialized to a known value. The AMD-762 system controller is reset when the Southbridge's PCIRST# pin is asserted, which occurs when transitioning from the Mechanical Off, S5, S4, or S3 sleep states. To accommodate support of the Advanced Configuration and Powe r I n t e r f a ce ( AC P I ) S 3 ( s u s p e n d t o R A M ) p owe r management state, the registers listed in Table 1 on page 5 are not initialized to a known state after reset (RESET# asserted), and they must be initialized by BIOS after initial power-on for proper operation. These registers retain the value programmed by BIOS after subsequent assertions of the RESET# pin when transitioning to and from the S3 sleep state. 4 Overview Chapter 1 Preliminary Information 24462D--March 2002 AMD-762TM System Controller Software/BIOS Design Guide Table 1. AMD-762TM System Controller Configuration Register Bits Unknown at RESET# Register Name ECC Mode/Status Offset Dev 0:F0:0x48 Bit Name SERR_Enable ECC_Diag ECC_Mode SBPWaitState Addr_Timing_A Addr_Timing_A RD_Wait_State Reg_DIMM_En tWTR tWR DRAM Timing Dev 0:F0:0x54 tRRD Idle_Cyc_Limit PH_Limit tRC tRP tRAS tCL tRCD Burst_Ref_En Ref_Dis Reserved Cyc_Per_Ref CS7_X4Mode CS6_X4Mode CS5_X4Mode CS4_X4Mode CS3_X4Mode CS2_X4Mode CS1_X4Mode CS0_X4Mode Self_Ref_En CS_Base CS_Mask Addr_Mode CS_En Bit(s) [15:14] [12] [11:10] [31] [30] [29] [28] [27] [26] [25:24] [23] [18:16] [15:14] [11:9] [8:7] [6:4] [3:2] [1:0] [20] [19] [18] [17:16] [7] [6] [5] [4] [3] [2] [1] [0] [18] [31:23] [15:7] [2:1] [0] DRAM Mode/Status Dev 0:F0:0x58 Status/Control Memory Base Address 0-7 Dev 0:F0:0x70 Dev 0:F0:0xC0 through Dev 0:F0:0xDC Chapter 1 Overview 5 Preliminary Information AMD-762TM System Controller Software/BIOS Design Guide 24462D--March 2002 Table 1. AMD-762TM System Controller Configuration Register Bits Unknown at RESET# (Continued) Register Name Offset Bit Name SW_Recal Use_Act_Dly Auto_Cal_En Act_Dly_Inh Auto_Cal_Period Clk_Dly SW_Cal_Dly Cal_Dly Act_Dly PSlewMDAT NSlewMDAT PDrvMDAT NDrvMDAT PSlewDQS NSlewDQS PDrvDQS NDrvDQS PSlewCLK NSlewCLK PDrvCLK NDrvCLK PSlewCS NSlewCS PDrvCS NDrvCS PSlewCMDB NSlewCMDB PDrvCMDB NDrvCMDB PSlewCMDA NSlewCMDA PDrvCMDA NDrvCMDA Bit(s) [7] [6] [5] [4] [1:0] [31:24] [23:16] [15:8] [7:0] [29:27] [26:24] [19:18] [17:16] [13:11] [10:8] [3:2] [1:0] [29:27] [26:24] [19:18] [17:16] [13:11] [10:8] [3:2] [1:0] [29:27] [26:24] [19:18] [17:16] [13:11] [10:8] [3:2] [1:0] DDR PDL Calibration Control Dev 0:F1:0x40 DDR PDL Configuration 0-17 Dev 0:F1:0x44 through Dev 0:F1:0x88 DDR DQS/MDAT Pad Configuration Dev 0:F1:0x8C DDR CLK/CS Pad Configuration Dev 0:F1:0x90 DDR CMDB/CMDA Pad Configuration Dev 0:F1:0x94 6 Overview Chapter 1 Preliminary Information 24462D--March 2002 AMD-762TM System Controller Software/BIOS Design Guide Table 1. AMD-762TM System Controller Configuration Register Bits Unknown at RESET# (Continued) Register Name Offset Bit Name PSlewMAB NSlewMAB PDrvMAB NDrvMAB PSlewMAA NSlewMAA PDrvMAA NDrvMAA Bit(s) [29:27] [26:24] [19:18] [17:16] [13:11] [10:8] [3:2] [1:0] DDR MAB/MAA Pad Configuration Dev 0:F1:0x98 Refer to Section 7 on page 219 for suggested values for these configuration registers. 1.1.4 Programming Reserved Bits The AMD-762 system controller has many bits that are specified as reserved and which may be used in future silicon revisions. BIOS must always write a 0 to these bits and not depend on the value read back. 1.1.5 Power Management Considerations There are several requirements for BIOS initialization of the AMD-762 system controller's configuration register when supporting power management. Refer to Section 4 on page 193 for further details of these requirements. For any system enabling the S3 state, a number of core logic PCI configuration registers and processor MSRs must be saved or restored prior to suspending or restoring S3. Also, certain hidden bits must be unmasked. These requirements apply to all platforms regardless of segment and whether or not AMD PowerNow!TM is used. Chapter 1 Overview 7 Preliminary Information AMD-762TM System Controller Software/BIOS Design Guide 24462D--March 2002 1.2 Recommended AMD AthlonTM Processor SYS_CONFIG Settings Table 2 provides recommendations for settings in the AMD Athlon processor System Configuration register in systems that utilize the AMD-762 system controller. Table 2. Recommended Settings for AMD AthlonTM Processor SYSCFG Register Name BIOS Setting 0 Comments An Evict command, when set, is sent as part of an INVD instruction. The Evict command has no function in the AMD-762TM system controller. A LockToggle command, when set, is sent as part of a LOCK instruction prefix and certain other instructions. The AMD AthlonTM processor and the AMD-762 system controller support Change-To-Dirty commands. SysFillValIsD1, when set, causes the AMD Athlon processor to sample the SysFillValid during the D1 data window. When this bit is cleared, the AMD Athlon processor samples during the D0 data window. Clearing this bit generally increases performance. The reset state is cleared. ClVicBlkEn, when set, causes all evicted clean blocks to cause the CleanVictimBlk system interface command. This setting has no function with the AMD-762 system controller. There are three set-to-dirty enables: SetDirtyEnE, SetDirtyEnO, and SetDirtyEnS. If a given enable is set and a cache block must make a transition from E-to-M, O-toM, or S-to-M, then the AMD Athlon processor performs the action indicated by the setting of the ChxToDirtyDis field. However, if a given enable is cleared, the processor takes no externally visible action when the desired transition is performed. Bit Field [22] EvictEn [17] [16] SysUcLockEn ChxToDirtyDis 1 0 [13] SysFillValIsD1 0 [11] ClVicBlkEn SetDirtyEnE SetDirtyEnO 0 1 0 [10:8] SetDirtyEnS 1 8 Overview Chapter 1 Preliminary Information 24462D--March 2002 AMD-762TM System Controller Software/BIOS Design Guide 2 AMD-762TM System Controller Programmer's Interface Overview The AMD-762TM system controller supports both x86 and AlphaTM processors that conform to the Socket2000 bus specification. Both processors share a compatible view of system memory and peripherals. Legacy x86 (IBM PC-AT) memory mappings are implemented by x86 processors (AMD AthlonTM processor) as shown in Figure 1. 2.1 AMD AthlonTM Processor Family x86 Processor PC Memory View Mapping Logic Same view of the system Socket2000 AMD Athlon Processor Family Alpha Processor Conventional Memory View Socket2000 Northbridge AMD-762TM System Controller Northbridge AMD-762 System Controller PCI Southbridge AMD-766TM and AMD-768TM Peripheral Bus Controllers PCI Southbridge AMD-766 and AMD-768 Peripheral Bus Controllers Figure 1. AMD AthlonTM Processor Family Address Mapping Chapter 2 AMD-762TM System Controller Programmer's Interface 9 Preliminary Information AMD-762TM System Controller Software/BIOS Design Guide 24462D--March 2002 2.2 Address Map Table 3 shows the address map implemented by the AMD-762TM system controller. Table 3. AMD-762TM System Controller Socket2000 Memory Map Address Space End SysAddOut MSB =0 & 3 FFFF FFFF SysAddOut MSB =0 & 1 FEFF FFFF SysAddOut MSB =0 & 1 FDFF FFFF Name/Command Reserved (Masked) PCI Configuration Space (Masked) PCI I/O Space (Masked) Description May be used by the Northbridge for other purposes (used for EV6 Northbridges). This space is used to create PCI configuration cycles using WrBytes, WrLWs, RdBytes, and RdLWs commands only. See Section 2.2.3 on page 15. This space is used to create PCI I/O cycles using only WrBytesWrLWs, RdBytes and RdLWs commands. WrLWs commands to this space are used to create PCI special cycles. The lower 16 bits of the data is passed on to the PCI bus as both the address and data with the special cycle PCI command. See Section 2.2.1 on page 12 for all special cycles generated by the AMD AthlonTM processor. RdBytes commands to this space are used to create PCI IACK. The lower 16 bits of these addresses are passed on unmodified to the PCI with the IACK PCI command. See Section 2.2.2 on page 15. May be used by the Northbridge for other purposes (used for EV6 Northbridges). The lower 32 bits of these addresses are forwarded unmodified to the PCI. Accessed only with Wr/RdBytes, Wr/RdLWs, Wr/RdQWs. The AMD-762TM system controller generates low-order address bit as required from the AMD Athlon processor system bus MASK field. DRAM, accessed only with masked write commands WrBytes, WrLWs, WrQWs. The AMD-762 system controller does not support masked reads to this address space. May be used by the Northbridge for other purposes (used for EV6 Northbridges). DRAM, accessed with read and write block commands. Note that the AMD-762 system controller only uses 32 address bits internally and the address space wraps. Address 1 0000 0000 is treated the same as 0 0000 0000. Address Space Start SysAddOut MSB =0 & 1 FF000 0000 SysAddOut MSB =0 & 1 FE00 0000 SysAddOut MSB =0 & 1 FC00 0000 SysAddOut MSB =0 SysAddOut MSB & =0 & 1 F800 0000 1 FBFF FFFF PCI IACK/Special Cycle Generation (Masked) SysAddOut MSB =0 SysAddOut MSB & =0 & 1 0000 0000 1 F7FF FFFF SysAddOut MSB =0 SysAddOut MSB & =0 & 0 0000 0000 0 FFFF FFFF SysAddOut MSB =1 & 0 0000 0000 SysAddOut MSB =1 & 0 0000 0000 SysAddOut MSB =1 & 0 FF000 0000 SysAddOut MSB =1 & 3 FFFF FFFF SysAddOut MSB =1 & 3 FFFF FFFF SysAddOut MSB =1 & 3 FFFF FFFF Reserved (Masked) PCI Memory Space (Masked) Normal Memory (Masked Writes) Reserved (Masked Reads) Reserved (Blocks) Normal Memory (Blocks) SysAddOut MSB =0 SysAddOut MSB & =0& 0 0000 0000 3 FFFF FFFF 10 AMD-762TM System Controller Programmer's Interface Chapter 2 Preliminary Information 24462D--March 2002 AMD-762TM System Controller Software/BIOS Design Guide For reference, the x86 view of memory from the perspective of the AMD Athlon processor and the mapping to the Socket2000 memory map is shown in Figure 2. Note: Not to scale. I/O Space CF8, CFC x86 In and Out Address Space APIC Registers Reserved PCI Memory PCI Config PCI I/O Reserved PCI IACK/Special AGP Virtual (BAR0) Reserved TOM GART Extended Memory PCI Memory DRAM BIOS VGA DOS Memory 640-1-Mbyte addresses are sent to PCI or DRAM as a function of AMD AthlonTM processor MSRs. x86 Memory Address Space Socket2000 Address Space Figure 2. Chapter 2 AMD AthlonTM Processor Family x86 Processor Address Mapping AMD-762TM System Controller Programmer's Interface 11 Preliminary Information AMD-762TM System Controller Software/BIOS Design Guide 24462D--March 2002 2.2.1 Special Cycles Special cycles generated by the AMD Athlon processor are forwarded down to the PCI bus with specific values in the address and data fields of the PCI special cycle command. Table 4 defines these values. The AMD Athlon processor g e n e ra t e s A M D A t h lo n p ro c e ss o r s y s t e m b u s W r LW s commands to a single address (1 F8000 0000) with the data field specifying the desired special cycle. The AMD-762 system controller maps the AMD Athlon processor system bus data value onto the PCI for both address and data phases of the Special Cycle Transaction. . Table 4. AMD AthlonTM Processor Special Cycle Encodings PCI Address and Data Field Contents Processor Description Northbridge and Southbridge Description The AMD-762TM system controller forwards onto the PCI bus the PCI special cycle command: AD[31:0] = 0000 0000 (address and data). AMD-768TM and AMD-766TM peripheral bus controllers assert INIT to processor(s). The AMD-762 system controller forwards onto the PCI bus. PCI special cycle command: AD[31:0] = 0000 0001 (address and data) AMD-768 and AMD-766 peripheral bus controllers ignore. The AMD-762 system controller forwards onto the PCI bus, PCI special cycle command: AD[31:0] = 0001 0002 (address and data). AMD-768 and AMD-766 peripheral bus controllers ignore. The AMD-762 system controller forwards onto the PCI bus the PCI special cycle command: AD[31:0] = 0002 0002 (address and data). AMD-768 and AMD-766TM peripheral bus controllers ignore. Special Cycle SHUTDOWN 0000 0000 The AMD AthlonTM processor generates in response to a shutdown condition. AMD Athlon processor system bus WrLWs command: SysAddOut: MSB=0 & [33:0] = 1 F8000 0000 SysDatOut: [31:0] = 0000 0000 HALT 0000 0001 The AMD Athlon processor generates in response to executing a HALT instruction: WrLWs command: SysAddOut: MSB=0 & [33:0] = 1 F8000 0000 SysDatOut: [31:0] = 0000 0001 The AMD Athlon processor generates in response to executing a WBINV instruction WrLWs command: SysAddOut: MSB=0 & [33:0] = 1 F8000 0000 SysDatOut: [31:0] = 0001 0002 The AMD AthlonTM processor generates in response to executing an INVD instruction WrLWs command: SysAddOut: MSB=0 & [33:0] = 1 F8000 0000 SysDatOut: [31:0] = 0002 0002 WB INVALIDATE 0001 0002 INVALIDATE 0002 0002 12 AMD-762TM System Controller Programmer's Interface Chapter 2 Preliminary Information 24462D--March 2002 AMD-762TM System Controller Software/BIOS Design Guide Table 4. AMD AthlonTM Processor Special Cycle Encodings (Continued) PCI Address and Data Field Contents Processor Description The AMD Athlon processor generates in response to assertion of the FLUSH pin after all caches have been flushed to memory. WrLWs command: SysAddOut: MSB=0 & [33:0] = 1 F8000 0000 SysDatOut: [31:0] = 0003 0002 The AMD Athlon processor generates CONNECT as the first cycle after STOP/GRANT or HALT AMD Athlon system bus special cycle regardless of whether or not a disconnect is achieved (or even attempted). WrLWs command: SysAddOut: MSB= 0 & [33: 0] = 1 F8000 0000 SysDatOut: [31: 0] = 0004 0002 The AMD Athlon processor generates an SMM ACK (ENTER) when entering a system management interrupt. WrLWs command: SysAddOut: MSB= 0 & [33: 0] = 1 F8000 0000 SysDatOut: [31: 0] = 0005 0002 The AMD Athlon processor generates SMM ACK (EXIT) when exiting from a system management interrupt. Northbridge and Southbridge Description The AMD-762TM system controller forwards onto the PCI bus, PCI special cycle command: AD[31:0] = 0003 0002 (address and data). AMD-768TM and AMD-766 peripheral bus controllers ignore. Special Cycle FLUSHACK 0003 0002 CONNECT 0004 0002 The AMD-762 forwards onto the PCI bus, PCI special cycle command: AD[31: 0] = 0004 0002 (address and data) AMD-768 and AMD-766 peripheral bus controllers ignore. SMM ACK (ENTER) 0005 0002 The AMD-762 system controller forward onto the PCI bus, special cycle command: AD[31: 0] = 0005 0002. SMM ACK (EXIT) 0006 0002 WrLWs command: SysAddOut: MSB= 0 & [33: 0] = 1 F8000 0000 SysDatOut: [31: 0] = 0006 0002 The AMD-762 system controller forwards to the PCI bus. Command: AD[31: 0] = 0006 0002 Chapter 2 AMD-762TM System Controller Programmer's Interface 13 Preliminary Information AMD-762TM System Controller Software/BIOS Design Guide 24462D--March 2002 Table 4. AMD AthlonTM Processor Special Cycle Encodings (Continued) PCI Address and Data Field Contents Processor Description Northbridge and Southbridge Description The AMD-762TM system controller waits for all queues to memory to be empty (assumes the PCI grant enable register is clear, "Dev0:F0:0x84" on page 78). The AMD-762 system controller optionally (via "Dev0:F0:0x60" on page 63) initiates an AMD Athlon processor system bus disconnect to this specific processor. The AMD-762 system controller forwards onto the PCI bus (after the optional system bus disconnect) PCI special cycle command: AD[31:0] = 0012 0002 (address and data). Only a single STOP GRANT special cycle is forwarded to the PCI bus. The AMD-768TM and AMD-766TM peripheral bus controllers receive and enter the appropriate power state. The AMD-768 and AMD-766 peripheral bus controllers may then assert DCSTOP# to the Northbridge to signal that it should deassert CKE to DDR SDRAMs and stop its internal clocks. Special Cycle STOP/GRANT 0012 0002 AMD AthlonTM processor generates in response to assertion of the STPCLK. WrLWs command: SysAddOut: MSB=0 & [33:0] = 1 F8000 0000 SysDatOut: [31:0] = 0012 0002 14 AMD-762TM System Controller Programmer's Interface Chapter 2 Preliminary Information 24462D--March 2002 AMD-762TM System Controller Software/BIOS Design Guide 2.2.2 IACK In x86 compatible Socket2000 systems, APIC is used as the interrupt controller. To fetch the appropriate vector during IACK cycles, x86 processors are required to assert their APIC ID (CPU ID) on bits [15:12] of the address field when reading the IACK generation space. IACK return data flushes all PCI and AGP/PCI write buffers to memory. 2.2.3 PCI Configuration Accesses In legacy x86 PC systems, PCI configuration cycles are generated via an indirect method. A configuration address register is defined at I/O address 0CF8 that allows software to load a value that is asserted on the PCI address wires during the next configuration read/write cycle. A configuration data register is defined at I/O address 0CFC that allows software to generate configuration read and write cycles on the PCI using IN and OUT instructions. Data sent during OUT instructions to the Configuration Data register is asserted on the PCI data wires during the generated configuration write transaction. Data received in response to a generated configuration read transaction is returned to satisfy the IN from the Configuration Data register. In Socket2000 systems, PCI configuration cycles are generated in one of two ways: In EV6 Compatible mode, the x86 processor must detect IN and OUT instructions that reference 0CF8 and 0CFC and generate the appropriate, explicit RdBytes/Rd/LWs and WrBytes/WrLWs Socket2000 commands to a 16-Mbyte region as follows: * When an OUT instruction is detected to 0CF8, the write data is saved into a register and the instruction retired. * When an IN/OUT instruction is detected to 0CFC, an appropriate AMD Athlon system bus Rd/Wr transaction is launched with the SysAdd Field[23:0] taken from the register that saved the most recent write to 0CF8 (above). In traditional mode, which the AMD-762 system controller implements, IN and OUT instructions that reference 0CF8 and 0CFC are passed normally on to the AMD Athlon processor system bus where the Northbridge generates the appropriate PCI configuration access. 15 Chapter 2 AMD-762TM System Controller Programmer's Interface Preliminary Information AMD-762TM System Controller Software/BIOS Design Guide 24462D--March 2002 2.3 Address Decoding A consistent view of memory and PCI devices is enforced by decoding logic in the AMD-762TM system controller in the AMD Athlon processor system bus and PCI interfaces. 2.3.1 Socket2000 Address Decoding The AMD-762 system controller must consider both the AMD Athlon processor system bus SysAddOut field and the command field when deciding what to do with a given command. This AMD Athlon processor system bus decoding is summarized as follows: SysAddOut MSB = 0 and command is a block command, DRAM is accessed: * If SysAddOut [31:0] falls between Dev0:BAR0 and Dev0:BAR0+Len, address is to AGP virtual address space and needs to passed through the GART before presentation to DRAM. SysAddOut MSB = 1 and command is a masked write command (WrQWs, WrLWs, WrBytes), DRAM is accessed: * If SysAddOut [31:0] falls between Dev0:BAR0 and Dev0:BAR0+Len, address is to AGP virtual address space and needs to passed through the GART before presentation to DRAM. SysAddOut MSB = 0 and SysAddOut [35:32] = 0 and command is a masked command, PCI memory-mapped I/O is accessed: * Using Dev0:F0:0x14, BAR1, send to the AMD-762 system controller memory-mapped GART control registers (see Section 2.5 on page 147). * Memory range address decoding, send to either PCI or AGP/PCI using address bits [31:0] based on the following: * Dev1:0x20, 0x24 (see "AGP/PCI Memory Limit and Base (Dev1:0x20)" on page 140 and "AGP/PCI Prefetchable Memory Limit and Base (Dev1:0x24)" on page 142). * Dev 0:F0:0x84 AGP VGA BIOS bits, see "Bit Definitions PCI Arbitration Control (Dev0:F0:0x84)" on page 79). Chapter 2 16 AMD-762TM System Controller Programmer's Interface Preliminary Information 24462D--March 2002 AMD-762TM System Controller Software/BIOS Design Guide SysAddOut MSB = 0 and SysAddOut [35:24] = 1F8 and command is RdBytes, an IACK special cycle is generated on the primary PCI. SysAddOut[15:0] are asserted on PCI AD[15:0] during this cycle. The data returned on the PCI is returned to the processor. SysAddOut MSB = 0 and SysAddOut [35:24] = 1F8 and command is WrBytes, a PCI special cycle is generated on the primary PCI. SysAddOut[15:0] are asserted on PCI AD[15:0] during this cycle (address = data). SysAddOut MSB = 0 and SysAddOut [35:24] = 1FC/1FD and command is RdBytes or WrBytes, a PCI I/O command is generated. SysAddOut[23:0] are asserted on PCI AD[23:0] with the PCI I/O read or write command. * Using Dev1:0x1C, I/O range address decoding, send to either PCI or AGP/PCI. Note: Low-order AMD Athlon processor system bus address bits, per the AMD Athlon processor system bus specification, SysAddOut only goes down to PA[3]. For mask operations, the Mask[7:0] bits are encoded to logically create PA[2:0] in the above. 2.3.2 PCI/AGP Master Address Decoding The PCI controllers in the AMD-762 system controller must consider the received PCI/AGP address in conjunction with the BAR registers and the memory configuration registers to route the transaction. The AMD-762 system controller does not allow PCI masters to access I/O regions or main memory from 640 Kbyte to 1 Mbyte (unless the EV6_Mode bit is set as described in "Bit Definitions PCI Arbitration Control (Dev0:F0:0x84)" on page 79). This decoding is summarized as follows: 1. AD[31:0] is less than the physical top of memory (from the memory controller), DRAM is accessed. 2. AD[31:0] is above the physical top of memory and it falls between Dev0:BAR0 and Dev0:BAR0+Len, address is to AGP virtual address space and needs to be passed through the GART before presentation to DRAM. Chapter 2 AMD-762TM System Controller Programmer's Interface 17 Preliminary Information AMD-762TM System Controller Software/BIOS Design Guide 24462D--March 2002 3. Memory range address decoding, send to AGP/PCI using address bits [31:0] based on the following (for writes only from the primary PCI): * Dev1:0x20, 0x24 (see "AGP/PCI Memory Limit and Base (Dev1:0x20)" on page 140 and "AGP/PCI Prefetchable Memory Limit and Base (Dev1:0x24)" on page 142). * Dev 0:F0:0x84 AGP VGA BIOS bits (see "Bit Definitions PCI Arbitration Control (Dev0:F0:0x84)" on page 79). 4. Else, the primary PCI is accessed (for writes only from the AGP/PCI). Note: GART Control register access. The AMD-762 system controller does not allow access to the memory-mapped GART control registers from either PCI or AGP/PCI masters. 2.4 Configuration Registers All functional registers in the AMD-762 system controller are implemented as PCI configuration registers. The AMD-762 system controller implements a standard PCI hierarchy that allows BIOS software to enumerate devices on the primary PCI, the AGP port, and future interfaces. See the logical bus hierarchy in Figure 3 on page 19. Note that the AMD-762 system controller only responds to function 0 and 1, device 0 and function 0, device 1. All other configuration accesses return Fs. Function 1, device 0 accesses are ignored unless enabled by the appropriate bit in the PCI Control register (see "Dev0:F0:0x4C" on page 48). 18 AMD-762TM System Controller Programmer's Interface Chapter 2 Preliminary Information 24462D--March 2002 AMD-762TM System Controller Software/BIOS Design Guide Processor Processor 2 Processor System Only Host to PCI Bridge Device 0:F0/F1 PCI PCI Devices Southbridge PCI-to-PCI Bridge Device 1:F0 PCI-to-PCI Bridge Device 1:F1 AGP AGP Master (Future Interface) Figure 3. AMD-762TM System Controller Logical Bus Hierarchy Chapter 2 AMD-762TM System Controller Programmer's Interface 19 Preliminary Information AMD-762TM System Controller Software/BIOS Design Guide 24462D--March 2002 2.4.1 I/O Register Map The AMD-762 system controller implements some I/O registers (accessed by processor I/O instructions). These registers, as presented in Table 5, are the Configuration Address and Configuration Data registers as specified in PCI Local Bus Specification, Revision 2.2. Table 5. I/O Register Map AMD AthlonTM Processor System Bus Address SysAddOut MSB =0 & 1 FC000 0CF8 SysAddOut MSB =0 & 1 FC000 0CFC Reference "I/O:0CF8" on page 21 and "I/O:0CF8" on page 23 "I/O:0CFC" on page 25 Register Configuration Address Configuration Data 20 AMD-762TM System Controller Programmer's Interface Chapter 2 Preliminary Information 24462D--March 2002 AMD-762TM System Controller Software/BIOS Design Guide Configuration Address Register Type 0 31 Bit Reset R/W Config_En 0 R/W 23 Bit Reset R/W 15 Bit Reset R/W 7 Bit Reset R/W 0 0 0 R/W 6 5 Reg_Num 0 0 0 0 R 4 0 0 14 13 Dev_Num 0 0 R/W 3 2 1 0 0 12 0 0 0 22 21 20 0 0 0 30 29 28 27 Reserved 0 R 19 18 17 0 0 26 25 I/O:0CF8 24 0 16 PCI_Bus_Num 0 R/W 11 10 9 Func_Num 0 0 8 0 0 0 0 0 Reserved 0 Register Description When writes to the configuration address register have [23:16] == 0h00, a Type 0 configuration access is specified. Chapter 2 AMD-762TM System Controller Programmer's Interface 21 Preliminary Information AMD-762TM System Controller Software/BIOS Design Guide 24462D--March 2002 Bit Definitions Bit 31 Name Config_En Function Configuration Address Register Type 0 (I/O:0CF8) Configuration Enable 0 = PCI configuration cycles are not generated. 1 = Accesses to the Configuration Data and Address registers are converted to configuration cycles on the PCI. 30-24 23--16 Reserved PCI_Bus_Num Reserved PCI Bus Number This bit field defines which PCI bus in the system is referenced with this address. The AMD-762TM system controller logically implements two PCI buses. The main PCI bus normally enumerates as bus 0 and the AGP bus enumerates as bus 1. Device Number This bit field defines which device is accessed in the system. Devices are assigned numbers in a system by tying the device IDSEL wire to a specific PCI AD wire. The AMD-762 system controller decodes this field and asserts the appropriate AD wire during the address phase to select the defined device. In the AMD-762 system controller there are two "hard-wired" device numbers for the host to PCI bridge (0b00000) and P2P bridge (0b00001). Function Number This bit field defines which function is accessed in a given device. The AMD-762 system controller responds to function 0 only (0b000) by default. Function 1 (DDR PDL registers) can be enabled via writing to the PCI Control register (Dev 0:F0:0x4C) as described on page 48. Register Number This bit field defines which specific PCI register is accessed in the device and function specified above. The register numbers for the AMD-762 system controller device 0 are listed in Table 6, "Device 0, Function 0 Configuration Register Map," on page 27. The register numbers for the AMD-762 device 1 are listed in Table 15, "Device 1 Configuration Register Map," on page 126. Reserved 15--11 Dev_Num 10--8 Func_Num 7--2 Reg_Num 1--0 Reserved Programming Notes 22 AMD-762TM System Controller Programmer's Interface Chapter 2 Preliminary Information 24462D--March 2002 AMD-762TM System Controller Software/BIOS Design Guide Configuration Address Register Type 1 31 Bit Reset R/W Config_En 0 R/W 23 Bit Reset R/W 15 Bit Reset R/W 7 Bit Reset R/W 0 0 0 R/W 6 5 Reg_Num 0 0 0 0 R 4 0 0 14 13 Dev_Num 0 0 R/W 3 2 1 0 0 12 0 0 0 22 21 20 0 0 0 30 29 28 27 Reserved 0 R 19 18 17 0 0 26 25 I/O:0CF8 24 0 16 PCI_Bus_Num 0 R/W 11 10 9 Func_Num 0 0 8 0 0 0 0 0 Reserved 0 Register Description When writes to the configuration address register have [23:16] ~= 0h00, a type 1 configuration access is specified. Chapter 2 AMD-762TM System Controller Programmer's Interface 23 Preliminary Information AMD-762TM System Controller Software/BIOS Design Guide 24462D--March 2002 Bit Definitions Bit 31 Name Config_En Function Configuration Address Register Type 1 (I/O:0CF8) Configuration Enable 0 = PCI configuration cycles are not generated. 1 = Accesses to the Configuration Data and Address registers are converted to configuration cycles on the PCI. 30-24 23--16 Reserved PCI_Bus_Num Reserved PCI Bus Number This bit field defines which PCI bus in the system is referenced with this address. The AMD-762TM system controller logically implements two PCI buses. The main PCI bus normally enumerates as bus 0 and the AGP bus enumerates as bus 1. Device Number This bit field defines which device is accessed in the system on the target PCI bus. This field is passed on directly to the AD wires undecoded. Function Number This bit field defines which function is accessed in a given device. This field is passed on directly to the AD wires undecoded. Register Number This bit field defines which specific PCI register is accessed in the device and function specified above. Reserved 15--11 Dev_Num 10--8 Func_Num 7--2 Reg_Num 1--0 Reserved Programming Notes 24 AMD-762TM System Controller Programmer's Interface Chapter 2 Preliminary Information 24462D--March 2002 AMD-762TM System Controller Software/BIOS Design Guide Configuration Data 31 Bit Reset R/W 23 Bit Reset R/W 15 Bit Reset R/W 7 Bit Reset R/W x x x x R/W 6 5 4 Config_Data x x x x x x x R/W 3 2 1 14 13 12 x x x x R/W 11 10 9 22 21 20 x x x x R/W 19 18 17 30 29 28 27 26 25 Config_Data x x x I/O:0CFC 24 x 16 Config_Data x x x x 8 Config_Data x x x x 0 x Register Description Bit Definitions Bit 31--0 Name Config_Data Function Configuration Data (I/O:0CFC) Configuration Data This bit field is used to access the PCI configuration register specified in the Configuration Address register above. Programming Notes Chapter 2 AMD-762TM System Controller Programmer's Interface 25 Preliminary Information AMD-762TM System Controller Software/BIOS Design Guide 24462D--March 2002 2.4.2 Configuration Register Access The AMD-762TM system controller implements most registers as PCI configuration registers. The x86 software executes IN and OUT instructions to I/O addresses of 0CF8 and 0CFC to access all configuration registers. These are translated by the AMD AthlonTM processor into AMD Athlon processor system bus RdBytes and WrBytes commands with the lower 24 bits of the address field containing the logical contents of the ConfigAddr register (I/O address 0CF8). The format of this register is shown in "I/O:0CF8" on page 21 and "I/O:0CF8" on page 23. Configuration accesses in the AMD-762 system controller conform to the following rules: The AMD-762 system controller is defined to be function 0 and 1, device 0; and function 0, device 1. The IDSEL pin of all external PCI devices must be wired to 1 of AD[31:13] as logically [12:11] are assigned to device 0, 1 (AMD-762 system controller). Function 1, device 0 configuration space contains only the DDR Programmable Delay Line (PDL) registers. This space is enabled only when the appropriate bit is set in the PCI Control register (see "Dev0:F0:0x4C" on page 48). Accesses to the normal reserved PCI space of function 1 yields all 1s. Accesses to function 1 are ignored when function 1 is not enabled. Device 0 accesses correspond to the host to PCI bridge registers defined in Section 2.4.3 on page 27. Device 1 accesses correspond to the PCI-to-PCI bridge registers defined in Section 2.4.5 on page 126. Access can be byte, word or DWord in length and must be naturally aligned. Northbridges are required to create type 0 and type 1 accesses as follows: If SysAdd[23:16] = 0 (Bus# = 2'h00), a type 0 config cycle is generated and PCI AD[1:0] = 2'b00. Device#, SysAdd[15:11] is decoded and asserted on PCI AD[31:11] for IDSEL. If SysAdd[23:16] != 0 (Bus# != 2'h00), a type 1 config cycle is generated and PCI AD[1:0] = 2'b01. Bus# and Device# fields are passed onto the PCI directly with no decoding. PCI AD[31:24] = 2'h00. Chapter 2 26 AMD-762TM System Controller Programmer's Interface Preliminary Information 24462D--March 2002 AMD-762TM System Controller Software/BIOS Design Guide 2.4.3 Device 0: PCI Configuration Registers In Table 6, the column entitled Offset consists of the register number specified in the Configuration Address register bits [7:2] concatenated with 0b00 to form a simple 1-byte offset. Reserved configuration registers return 0 when read. Table 6. Device 0, Function 0 Configuration Register Map Host to PCI Bridge (Device 0, Function 0) Device ID Status Class Code = 0x060000 Vendor ID Command Revision ID Latency Timer Reserved Offset 0x00-0x03 0x04-0x07 0x08-0x0B 0x0C-0x0F 0x10-0x13 0x14-0x17 0x18-0x1B 0x1C-0x33 Capabilities Pointer: A0 Reserved Extended BIU Control ECC Mode/Status PCI Control AMD AthlonTM Processor System Bus Dynamic Compensation DRAM Timing DRAM Mode/Status 0x34-0x37 0x38-0x43 0x44-0x53 0x48-0x4B 0x4C-0x4F 0x50-0x53 0x54-0x57 0x58-0x5B 0x5C-0x5F BIU0 Status/Control BIU0 SIP 0x60-0x63 0x64-0x67 "Dev0:F0:0x60" on page 63 "Dev0:F0:0x64" on page 66 "Dev0:F0:0x44" on page 42 "Dev0:F0:0x48" on page 45 "Dev0:F0:0x4C" on page 48 "Dev0:F0:0x50" on page 51 "Dev0:F0:0x54" on page 53 "Dev0:F0:0x58" on page 58 "Dev0:F0:0x34" on page 41 Reference "Dev0:F0:0x00" on page 30 "Dev0:F0:0x04" on page 32 "Dev0:F0:0x08" on page 35 "Dev0:F0:0x0C" on page 36 "Dev0:F0:0x10" on page 37 "Dev0:F0:0x14" on page 39 Reserved Header Type BAR0 - AGP Virtual Address Space BAR1 - GART Memory-Mapped Control Registers Pointer Reserved Reserved Reserved Chapter 2 AMD-762TM System Controller Programmer's Interface 27 Preliminary Information AMD-762TM System Controller Software/BIOS Design Guide 24462D--March 2002 Table 6. Device 0, Function 0 Configuration Register Map (Continued) Host to PCI Bridge (Device 0, Function 0) BIU1 Control BIU1 SIP Memory Status/Control Offset 0x68-0x6B 0x6C-0x6F 0x70-0x73 0x74-0x77 0x78-0x7B 0x7C-0x7F Reserved Boot Proc PCI Arbitration Control Configuration Status WHAMI 0x80-0x83 0x84-0x87 0x88-0x8B 0x8C-0x8F 0x90-0x93 0x94-0x97 0x98-0x9B PCI Top of Memory AGP Capability Identifier AGP Status AGP Command AGP Virtual Address Space Size GART/AGP Mode Control AGP 4X Dynamic Compensation AGP Compensation Bypass 0x9C-0x9F 0xA0-0xA3 0xA4-0xA7 0xA8-0xAB 0xAC-0xAF 0xB0-0xB3 0xB4-0xB7 0xB8-0xBF 0xC0-0xC3 0xC4-0xC7 0xC8-0xCB "Dev0:F0:0x9C" on page 86 "Dev0:F0:0xA0" on page 88 "Dev0:F0:0xA4" on page 89 "Dev0:F0:0xA8" on page 91 "Dev0:F0:0xAC" on page 93 "Dev0:F0:0xB0" on page 95 "Dev0:F0:0xB4" on page 97 "Dev0:F0:0xB8" on page 100 "Dev0:F0:0xC0" on page 104 "Dev0:F0:0xC4" on page 104 "Dev0:F0:0xC8" on page 104 "Dev0:F0:0x80" on page 76 "Dev0:F0:0x84" on page 78 "Dev0:F0:0x88" on page 82 Reference "Dev0:F0:0x68" on page 68 "Dev0:F0:0x6C" on page 71 "Dev0:F0:0x70" on page 74 28 AMD-762TM System Controller Programmer's Interface Chapter 2 Preliminary Information 24462D--March 2002 AMD-762TM System Controller Software/BIOS Design Guide Table 6. Device 0, Function 0 Configuration Register Map (Continued) Host to PCI Bridge (Device 0, Function 0) Offset 0xCC-0xCF 0xD0-0xD3 0xD4-0xD7 0xD8-0xDB 0xDC-0xDF Reserved 0xE0-0xFF Reference "Dev0:F0:0xCC" on page 104 "Dev0:F0:0xD0" on page 104 "Dev0:F0:0xD4" on page 104 "Dev0:F0:0xD8" on page 104 "Dev0:F0:0xDC" on page 104 Chapter 2 AMD-762TM System Controller Programmer's Interface 29 Preliminary Information AMD-762TM System Controller Software/BIOS Design Guide 24462D--March 2002 PCI ID 31 Bit Reset R/W 23 Bit Reset R/W 15 Bit Reset R/W 7 Bit Reset R/W 0 0 1 0 R 6 5 4 Vend_ID 0 0 1 0 0 0 1 R 3 2 1 14 13 12 Vend_ID 0 0 0 0 0 0 0 R 11 10 9 22 21 20 Dev_ID 1 1 0 0 1 1 1 R 19 18 30 29 28 Dev_ID 0 0 0 27 26 Dev0:F0:0x00 25 24 0 17 16 0 8 0 0 0 Register Description 30 AMD-762TM System Controller Programmer's Interface Chapter 2 Preliminary Information 24462D--March 2002 AMD-762TM System Controller Software/BIOS Design Guide Bit Definitions Bit 31--16 Name Dev_ID Function PCI ID (Dev0:F0:0x00) Device Identifier This 16-bit field is assigned by the device manufacturer and identifies the type of device. The current Northbridge device ID assignments are: AMD-761TM system controller -- AMD AthlonTM processor, 1P DDR 133 MHz 0x700E host to PCI bridge 0x700F PCI-to-PCI bridge (4-X AGP) AMD-762TM system controller -- AMD Athlon processor, 2P DDR 133 MHz 0x700C host to PCI bridge 0x700D PCI-to-PCI bridge (4-X AGP) AMD-751TM system controller -- AMD Athlon processor, 1P SDRAM-100 0x7006 host to PCI bridge 0x7007 PCI-to-PCI bridge (1X/2X AGP) 15--0 Vend_ID Vendor Identifier This 16-bit field identifies the manufacturer of the device. Programming Notes Chapter 2 AMD-762TM System Controller Programmer's Interface 31 Preliminary Information AMD-762TM System Controller Software/BIOS Design Guide 24462D--March 2002 PCI Command and Status 31 Bit Reset R/W PERR_Rcv 0 R 23 Bit Reset R/W 15 Bit Reset R/W 7 Bit Reset R/W STEP 0 6 PERR 0 5 VGA 0 R 0 0 0 14 13 Reserved 0 R 4 MWINV 0 3 SCYC 0 2 MSTR 1 1 0 0 12 Fast_B2B 0 30 SERR_Sent 0 R/W1C 22 UDF 0 29 Mas_ABRT 0 R/W1C 21 66M M66EN Pin 28 Trgt_ABRT 0 R/W1C 20 Cap_Lst 1 R 11 10 9 0 0 27 Trgt_ABRT _ Signaled 0 R 19 18 Reserved 0 26 Dev0:F0:0x04 25 24 Data_PERR 0 R 17 16 DEVSEL_Timing 0 R 1 0 8 SERR 0 R/W 0 I/O 0 R FBACK 0 MEM 0 R/W Register Description 32 AMD-762TM System Controller Programmer's Interface Chapter 2 Preliminary Information 24462D--March 2002 AMD-762TM System Controller Software/BIOS Design Guide Bit Definitions Bit 31 Name PERR_Rcv Function PCI Command and Status (Dev0:F0:0x04) Detected Parity Error This bit is always 0 because the AMD-762TM system controller does not support data parity checking. Signaled System Error This bit is set whenever the AMD-762 system controller generates a system error and asserts the SERR# line (ECC, GART error). This bit is cleared by writing a 1. Refer to Table 7 on page 34 for details about SERR# assertion and status. Received Master Abort This bit is set whenever a CPU to PCI transaction (except for a special cycle) is terminated due to a master abort. This bit is cleared by writing a 1. Received Target Abort This bit is set whenever a CPU to PCI transaction (except for a special cycle) is terminated due to a target abort. This bit is cleared by writing a 1. Signaled Target Abort This bit is always 0 because the AMD-762 system controller does not terminate transactions with target aborts. DEVSEL# Timing This bit field defines the timing of DEVSEL# on the AMD-762 system controller. The AMD-762 system controller supports medium DEVSEL# timing. Data Parity Error This bit is always 0 because the AMD-762 system controller does not report parity errors. Fast Back-to-Back Capable This bit is always 0, indicating that the AMD-762 system controller as a target is not capable of accepting fast back-to-back transactions when the transactions are not to the same agent. User-Definable Features This bit is always 0, indicating that UDF is not supported on the AMD-762 system controller. 66-MHz Capable The AMD-762 system controller sets this bit to indicate 66-MHz capability when the AD[15] pinstrap is High, enabling the 66-MHz PCI bus speed. Capabilities List This bit is set to indicate that this device's configuration space supports a capabilities list. Reserved Fast Back-to-Back to Different Devices Enable This bit is always 0, because the AMD-762 system controller does not allow generation of fast back-to-back transactions to different agents. 30 SERR_Sent 29 Mas_ ABRT 28 Trgt_ABRT 27 Trgt_ABRT_ Signaled DEVSEL_Timing 26--25 24 23 Data_PERR Fast B2B 22 UDF 21 66M 20 19-10 9 Cap_Lst Reserved FBACK Chapter 2 AMD-762TM System Controller Programmer's Interface 33 Preliminary Information AMD-762TM System Controller Software/BIOS Design Guide 24462D--March 2002 Bit Definitions (Continued) Bit 8 Name SERR Function System Error Enable 0 = SERR# driver disabled 1 = SERR# driver enabled PCI Command and Status (Dev0:F0:0x04) Refer to Table 7 for details about SERR# assertion and status. 7 STEP Address Stepping This bit is always 0 because the AMD-762TM system controller does not perform address stepping. Parity Error Response This bit is always 0 because the AMD-762 system controller does not report data parity errors. VGA Palette Snoop Enable This bit is always 0, indicating that the AMD-762 system controller does not snoop the VGA palette address range. Memory Write and Invalidate Enable This bit is always 0 because the AMD-762 system controller does not generate memory write and invalidate commands. Special Cycle This bit is always 0 because the AMD-762 system controller ignores PCI special cycles. Bus Master Enable This bit is always set, indicating that the AMD-762 system controller is allowed to act as a bus master on the PCI bus. Memory Access Enable 0 = PCI memory accesses ignored 1 = PCI memory accesses responded to 0 I/O I/O Access Enable This bit is always 0 because the AMD-762 system controller does not respond to I/O cycles on the PCI bus. 6 5 PERR VGA 4 MWINV 3 2 SCYC MSTR 1 MEM Programming Notes Table 7 lists the controls required to enable the assertion of the AMD-762 system controller SERR# pin and the various status bits that can be read to determine when the SERR# and A_SERR# pins have been asserted. Table 7. AMD-762TM System Controller SERR# Assertion Control and Status Bits SERR# Source SERR# Pin Assertion Control Enabled by bit 8, Dev 0:F0:0x04, PCI Status/Command register. Signalled System Error Status Bit Read bit 30, Dev 0:F0:0x04, PCI Status/Command register. Read bit 30, Dev 1:F0:0x1C, AGP/PCI Status, I/O and Base Limit, and bit 30, Dev 1:F0:0x04, AGP/PCI Command/Status. GART or ECC error Enabled by bit 8, Dev 1:F0:0x04, PCI Status/Command register, and bit 17, A_SERR# assertion on AGP interface forwarded to SERR# pin Dev 1:F0:0x3C, AGP/PCI Interrupt and Bridge Control. 34 AMD-762TM System Controller Programmer's Interface Chapter 2 Preliminary Information 24462D--March 2002 AMD-762TM System Controller Software/BIOS Design Guide PCI Revision ID and Class Code 31 Bit Reset R/W 23 Bit Reset R/W 15 Bit Reset R/W 7 Bit Reset R/W 0 0 0 6 5 Rev_ID 4 0 0 0 0 R 3 2 1 14 13 12 Prog_I/F 0 0 0 0 0 0 22 21 20 0 0 0 0 R 19 18 30 29 28 Class_Code 0 1 1 27 26 Dev0:F0:0x08 25 24 0 17 16 Sub-Class_Code 0 R 11 10 9 8 0 0 0 0 0 0 (See Programming Notes below.) 1 R 0 0 0 0 Register Description Bit Definitions Bit Name 31-24 Class_Code 23-16 15-8 7-0 SubClass_Code Prog_I/F Rev_ID PCI Revision ID and Class Code (Dev0:F0:0x08) Function Class Code Indicates a bridge device. Sub-Class Code Indicates a Host/PCI bridge. Program Interface Indicates a Host/PCI bridge. Revision Identification Identifies revision number of the device. Programming Notes Refer to the AMD-762TM System Controller Revision Guide, order# 24089, for details of the Rev_ID field for each silicon revision. Chapter 2 AMD-762TM System Controller Programmer's Interface 35 Preliminary Information AMD-762TM System Controller Software/BIOS Design Guide 24462D--March 2002 PCI Latency Timer and Header Type 31 Bit Reset R/W 23 Bit Reset R/W 15 Bit Reset R/W 7 Bit Reset R/W 0 0 0 0 R 6 5 4 Reserved 0 0 0 0 0 0 0 R/W 3 2 1 14 13 12 Lat_Timer 0 0 0 0 0 0 0 R 11 10 9 22 21 20 0 0 0 0 R 19 18 30 29 28 Reserved 0 0 0 27 26 Dev0:F0:0x0C 25 24 0 17 16 Header_Type 0 0 0 0 8 0 0 0 Register Description Bit Definitions Bit Name 31-24 Reserved 23-16 Header_Type PCI Latency Timer and Header type (Dev0:F0:0x0C) Function Reserved Header Type Bit 23 is always 0, indicating that the AMD-762TM system controller is a single function device. Bits [22:16] are 0, indicating that Type 00 configuration space header format is supported. Latency Timer This bit field defines the minimum amount of time in PCI clock cycles that the bus master can retain ownership of the bus. This action is mandatory for masters that are capable of performing a burst consisting of more than two data phases. Reserved 15-8 Lat_Timer 7-0 Reserved Programming Notes 36 AMD-762TM System Controller Programmer's Interface Chapter 2 Preliminary Information 24462D--March 2002 AMD-762TM System Controller Software/BIOS Design Guide Base Address 0: AGP Virtual Address Space 31 Bit Reset R/W 23 Bit Reset R/W 15 Bit Reset R/W 7 Bit Reset R/W 0 6 5 4 0 0 0 14 13 12 0 0 0 22 21 0 0 0 30 29 28 Base_Addr_High 0 R/W 20 19 18 17 0 0 0 27 26 25 Dev0:F0:0x10 24 BaseAddr_Low 0 R 16 Base_Addr_Low 0 R 11 10 9 8 0 0 0 0 Base_Addr_Low 0 R 3 Prefetchable 0 R 1 0 2 Type 0 1 0 Memory 0 0 0 0 0 Base_Addr_Low 0 0 Register Description This register is used by system BIOS memory mapping software to allocate virtual address space for AGP. Chapter 2 AMD-762TM System Controller Programmer's Interface 37 Preliminary Information AMD-762TM System Controller Software/BIOS Design Guide 24462D--March 2002 Bit Definitions Bit 31-25 Name Base_Addr_High Function Base Address 0: AGP Virtual Address Space (Dev0:F0:0x10) Base Address High This bit field forms the upper part of BAR0. This field is loaded by BIOS software. Note that when the GART enable bit in the AGP Virtual Address Space Size register is 0 (see "Dev0:F0:0xAC" on page 93), these bits always return 0s to indicate no address space should be allocated to AGP. Note that a write to this register must occur before a read returns 0s with the GART enable bit cleared. This bit field corresponds to bits [3:1] of the AGP Virtual Address Space Size register. When bits [3:1] of that register are set, the R/W attributes in bits [30:25] in this register are automatically set. BIOS software writes all 1s to this BAR register and then reads back the register to determine how much memory is required for AGP as follows: 31 RW RW RW RW RW RW RW 30 RW RW RW RW RW RW R 29 RW RW RW RW RW R R 28 RW RW RW RW R R R 27 RW RW RW R R R R 26 RW RW R R R R R 25 RW R R R R R R 32 Mbytes 64 Mbytes 128 Mbytes 256 Mbytes 512 Mbytes 1 Gbyte 2 Gbytes Memory 24-4 Base_Addr_Low Base Address Low This bit field is hardwired to return 0s to indicate that the minimum allocated memory size is 32 Mbytes. Prefetchable This bit is hardwired to 1 to indicate that this range is prefetchable. Type This bit field is hardwired to indicate that this base register is 32 bits wide and mapping can be performed anywhere in the 32-bit address space. Memory This bit is hardwired to 0 to indicate that this base address register maps into memory space. 3 2-1 Prefetchable Type 0 Memory Programming Notes 38 AMD-762TM System Controller Programmer's Interface Chapter 2 Preliminary Information 24462D--March 2002 AMD-762TM System Controller Software/BIOS Design Guide Base Address 1: GART Memory-Mapped Register Base 31 Bit Reset R/W 23 Bit Reset R/W 15 Bit Reset R/W 7 Bit Reset R/W 0 6 0 14 13 12 0 0 0 22 21 20 0 0 0 30 29 28 27 26 25 Base_Addr_High 0 R/W 19 18 17 0 0 0 Dev0:F0:0x14 24 0 16 Base_Addr_High 0 R/W 11 10 9 8 0 0 0 0 Base_Addr_High 0 R/W 5 4 3 Prefetchable 0 R 1 0 0 0 Base_Addr_Low 0 R 2 Type 0 0 1 0 Memory 0 0 0 Base_Addr_Low 0 0 Register Description This register provides the base address for the GART memory-mapped configuration register space (see "MemoryMapped Register Map" on page 149 for details). Chapter 2 AMD-762TM System Controller Programmer's Interface 39 Preliminary Information AMD-762TM System Controller Software/BIOS Design Guide 24462D--March 2002 Bit Definitions Bit 31-12 11-4 Name Base_Addr_High Base_Addr_Low Function Base Address 1: GART Memory-Mapped Register Base (Dev0:F0:0x14) Base Address High This bit field forms the upper part of BAR1. This field is loaded by BIOS software. Base Address Low This bit field is hardwired to return 0s to indicate that 4 Kbytes are allocated to GART memory-mapped control registers and that the registers always reside in a 4-Kbyte boundary per PCI Local Bus Specification, Revision 2.2. Prefetchable This bit is hardwired to 1 to indicate that this range is prefetchable Type This bit field is hardwired to indicate that this base register is 32 bits wide and mapping can be performed anywhere in the 32-bit address space. Memory This bit is hardwired to 0 to indicate that this base address register maps into memory space. 3 2-1 Prefetchable Type 0 Memory Programming Notes 40 AMD-762TM System Controller Programmer's Interface Chapter 2 Preliminary Information 24462D--March 2002 AMD-762TM System Controller Software/BIOS Design Guide AGP/PCI Capabilities Pointer 31 Bit Reset R/W 23 Bit Reset R/W 15 Bit Reset R/W 7 Bit Reset R/W 1 0 1 0 R 6 5 4 CAP_PTR 0 0 0 0 0 0 0 R 3 2 1 14 13 12 Reserved 0 0 0 0 0 0 0 R 11 10 9 22 21 20 Reserved 0 0 0 0 0 0 0 R 19 18 30 29 28 Reserved 0 0 0 27 26 Dev0:F0:0x34 25 24 0 17 16 0 8 0 0 0 Register Description Bit Definitions Bit 31-8 7-0 Name Reserved CAP_PTR Function Reserved AGP/PCI Capabilities Pointer (Dev0:0x34) Capabilities Pointer This field contains a byte offset into a device's configuration space containing the first item in the capabilities list. The first item in the capabilities list is the AGP function. Note that when the AGP valid bit in the PCI-to-PCI bridge virtual address space register is set to invalid, this capabilities pointer is set by the chipset to point to the next item in the linked list. If no next item exists, then it is set to null. Programming Notes Chapter 2 AMD-762TM System Controller Programmer's Interface 41 Preliminary Information AMD-762TM System Controller Software/BIOS Design Guide 24462D--March 2002 Extended BIU Control 31 Bit Reset R/W 23 Bit Reset R/W 15 Bit Reset R/W 7 Bit Reset R/W DWrDM 0 R/W 6 Reserved 0 R 5 Reserved 0 4 P1_2BitPF 0 R/W 0 Reserved 0 14 13 12 P1_WrDataDly SIP Stream R 3 P0_2BitPF 0 R/W 0 0 R 2 1 0 22 21 20 0 0 0 0 R 19 18 30 29 28 Reserved 0 0 0 27 26 Dev0:F0:0x44 25 24 0 17 16 P1_SRdDMEn 0 0 0 R/W 11 0 P0_SRdDMEn 0 0 0 10 9 P0_WrDataDly SIP Stream 8 0 0 Register Description This register provides controls for the processor interface, in addition to the BIU Control register at Dev 0:F0:0x60 for Processor 0 and Dev 0:F0:0x68 for Processor 1. P0_2BitPF and P1_2BitPF must be programmed to identical values for proper operation. 42 AMD-762TM System Controller Programmer's Interface Chapter 2 Preliminary Information 24462D--March 2002 AMD-762TM System Controller Software/BIOS Design Guide Bit Definitions Bit 31-24 23-20 Name Reserved P1_SRdDMEn Function Reserved Extended BIU Control (Dev0:F0:0x44) Speculative Read Data Movement Enable (Processor 1) In two processor systems ReadData commands are returned speculatively before the probe response is received. This may occur N clocks after the probe is sent if the memory data is available. N: 0000 Function Disabled N: 0001 One Clock N: 0010 Two Clocks ..... N: 1111 Fifteen Clocks The value programmed in this field must be identical to the value programmed in the P0_SRdDMEn field for Processor 0 for normal operation. Speculative Read Data Movement Enable (Processor 0) In two processor systems ReadData commands are returned speculatively, before the probe response is received. This may occur N clocks after the probe is sent if the memory data is available. N: 0000 Function Disabled N: 0001 One Clock N: 0010 Two Clocks ..... N: 1111 Fifteen Clocks The value programmed in this field must be identical to the value programmed in the P1_SRdDMEn field for Processor 1 for normal operation. Reserved Write Data Delay (Processor 1) WrDataDly is the time in SYSCLK periods from the launch of a SysDC WriteData command until the launch of the first data object by the processor. This value is a calculated part of the SIP Stream. This value is not provided in the BIU 1 SIP Register and is thus provided here. Write Data Delay (Processor 0) P0_WrDataDly is the time in SYSCLK periods from the launch of a SysDC WriteData command until the launch of the first data object by the processor. This value is a calculated part of the SIP stream. This value is not provided in the BIU 0 SIP register and is thus provided here. Defer Write Data Movement This bit enables a function which delays moving write data from the CPU when read data will be returned soon. In most circumstances, setting this bit will improve performance. 19-16 P0_SRdDMEn 15-14 13-11 Reserved P1_WrDataDly 10-8 P0_WrDataDly 7 DWrDM Chapter 2 AMD-762TM System Controller Programmer's Interface 43 Preliminary Information AMD-762TM System Controller Software/BIOS Design Guide 24462D--March 2002 Bit Definitions (Continued) Bit 6-5 4 Name Reserved P1_2BitPF Function Reserved Extended BIU Control (Dev0:F0:0x44) Two Bit Times Per Frame Enable (Processor 1) This bit enables use of the two bit time commands on the AMD AthlonTM processor system bus for Processor 1. This bit must be set when connected to an AMD Athlon and disabled when connected to an AlphaTM processor. For proper operation, BIOS must not clear this bit once it has been set. 0 = Two-bit time commands disabled 1 = Two-bit time commands enabled (AMD Athlon processor only) Two Bit Times Per Frame Enable (Processor 0) This bit enables the use of the two bit time commands on the AMD AthlonTM processor for Processor 0 processor system bus. This bit must be set when connected to an AMD Athlon processor and disabled when connected to an Alpha processor. For proper operation, BIOS must not clear this bit once it has been set. 0 = Two-bit time commands disabled 1 = Two-bit time commands enabled (AMD Athlon processor only) Reserved These bits must be written with 0 (cleared) for normal operation. 3 P0_2BitPF 2-0 Reserved Programming Notes P0_2BitPF and P1_2BitPF must be programmed to identical values for proper operation. 44 AMD-762TM System Controller Programmer's Interface Chapter 2 Preliminary Information 24462D--March 2002 AMD-762TM System Controller Software/BIOS Design Guide ECC Mode/Status 31 Bit Reset R/W 23 Bit Reset R/W 15 Bit Reset R/W 7 Bit Reset R/W 0 X R/W 6 14 13 Reserved X 0 R 5 12 ECC_Diag X R/W 4 3 X R/W 2 ECC_CS_SED 0 0 0 R 0 1 0 0 0 0 R 11 ECC_Mode X 0 10 9 22 21 20 Reserved 0 0 0 0 0 0 0 R 19 18 30 29 28 Reserved 0 0 0 27 26 Dev0:F0:0x48 25 24 0 17 16 0 8 ECC_Status 0 R/W1C 0 SERR_Enable ECC_CS_MED 0 R 0 0 Register Description This register provides ECC mode control and status reporting for the DRAM system. Note that some bits of this register are not initialized at reset time, and all bits must be initialized by BIOS for proper operation. This action should be done prior to attempting DRAM access. Chapter 2 AMD-762TM System Controller Programmer's Interface 45 Preliminary Information AMD-762TM System Controller Software/BIOS Design Guide 24462D--March 2002 Bit Definitions Bit 31-16 15-14 Name Reserved SERR_Enable Function Reserved ECC Mode/Status (Dev0:F0:0x48) System Error Enable These bits control the AMD-762TM system controller's reporting of ECC errors to the system via the SERR# pin on the PCI bus. Note that SERR# assertion is still subject to the normal PCI SERR# enable (bit 8 in Dev 0:F0:0x04). Refer to Table 7 on page 34 for details about SERR# assertion and status. 00 = SERR# assertion is disabled. X1 = Multiple bit errors force SERR# assertion. 1X = Single bit errors force SERR# assertion. 13 12 Reserved ECC_Diag Reserved Error Correcting Code Diagnostic Mode Enable 0 = ECC diagnostic mode disabled 1 = ECC diagnostic mode enabled When the ECC diagnostic mode is enabled, the AMD-762 system controller always writes 0x00 to the ECC byte to aid testing of the ECC logic. During partial writes, the RMW sequence still occurs, but the ECC bits are always written to 0x00. For reads, the ECC circuitry is unaffected by the ECC_Diag bit. The ECC code returned from memory is checked, and errors are reported in the ECC_Status bits as usual. Correction is not performed in this mode. 11-10 ECC_Mode Error Correcting Code Mode 00 = ECC disabled, no error detection or correction is performed. 01 = EC_HiPerf mode enabled. Error checking and status reporting is enabled. Data destined for the PCI/AGP and memory (RMR) is not corrected. 10 = ECC_HiPerf mode enabled. Error checking and status reporting is enabled. Data destined for the PCI/AGP and memory (RMR) is corrected. 11 = ECC_Scrub mode enabled. Error checking and status reporting is enabled. Data destined for the PCI/AGP and memory (RMR) is corrected. The memory contents are corrected (scrubbed) after all reads with errors. 9-8 ECC_Status Error Correcting Code Status This bit field indicates the status of the ECC detect logic as follows: 00 = No error X1 = MED: multi-bit error detect 1X = SED: single-bit error detect The ECC status bits and corresponding failing chip-select indicators are set by the first error detected of each type (SED or MED). The AMD-762 system controller does not log any new errors of each type or assert SERR# until software clears the associated ECC_Status bit by writing a 1. 46 AMD-762TM System Controller Programmer's Interface Chapter 2 Preliminary Information 24462D--March 2002 AMD-762TM System Controller Software/BIOS Design Guide Bit Definitions (Continued) Bit 7-4 Name ECC_CS_MED Function ECC Mode/Status (Dev0:F0:0x48) Multiple Bit Error Chip Select These bits provide the binary encoded chip select for the first multiple-bit error detected by the AMD-762TM system controller. Single Bit Error Chip Select These bits provide the binary encoded chip select for the first single-bit error detected by the AMD-762 system controller. 3-0 ECC_CS_SED Programming Notes System software is responsible for decoding the binary encoded, failing chip-select information and identifying a corresponding physical DIMM location. Some bits in this register are not initialized at reset. BIOS must initialize all bits in this register prior to attempting DRAM access. Chapter 2 AMD-762TM System Controller Programmer's Interface 47 Preliminary Information AMD-762TM System Controller Software/BIOS Design Guide 24462D--March 2002 PCI Control 31 Bit Reset R/W 23 Bit Reset R/W 15 Bit Reset R/W 7 Bit Reset R/W 0 Reserved 0 R 6 0 0 14 13 Reserved 0 R 5 M66EN Pin Value 4 Reserved 0 R 3 Reserved 0 R 0 0 12 0 0 0 0 R 11 10 Clk66Dis2 0 R/W 2 PCI_DT_En 0 R/W 9 22 21 20 Reserved 0 0 0 0 0 0 0 R 19 18 30 29 28 Reserved 0 0 0 27 26 Dev0:F0:0x4C 25 24 0 17 16 0 8 Clk66Dis0 0 R/W 0 Func1_En 0 R/W Clk66Dis1 0 R/W 1 PCI_OR_En 0 R/W Register Description This register controls various functions in the primary PCI and AGP interfaces. 48 AMD-762TM System Controller Programmer's Interface Chapter 2 Preliminary Information 24462D--March 2002 AMD-762TM System Controller Software/BIOS Design Guide Bit Definitions Bit 31--11 10 Name Reserved Clk66Dis2 Function Reserved PCI Control (Dev0:F0:0x4C) 66-MHz Clock Disable This bit field may be used to disable the PCI_66CLK2 (66-MHz PCI clock) output pin as desired. When disabled, the pin is forced low. 0 = PCI_66CLK2 pin enabled 1 = PCI_66CLK2 pin disabled Note: The clock pin connected to the Southbridge in 66-MHz mode must not be disabled. 66-MHz Clock Disable This bit field may be used to disable the PCI_66CLK1 (66-MHz PCI clock) output pin as desired. When disabled, the pin is forced low. 0 = PCI_66CLK1 pin enabled 1 = PCI_66CLK1 pin disabled Note: The clock pin connected to the Southbridge in 66-MHz mode must not be disabled. 66-MHz Clock Disable This bit field may be used to disable the PCI_66CLK0 (66-MHz PCI clock) output pin as desired. When disabled, the pin is forced low. 0 = PCI_66CLK0 pin enabled 1 = PCI_66CLK0 pin disabled Note that the clock pin connected to the Southbridge in 66-MHz mode must not be disabled! Reserved M66EN Pin Status This bit reflects the value of the PCI bus M66EN pin which indicates whether all installed devices support 66-MHz clock speeds. Reserved This bit must be written with 0s for normal operation. Reserved This bit must be written with 0s for normal operation. Delayed Transactions Enable (PCI) 0 = Delayed transactions disabled on the PCI interface 1 = Delayed transactions enabled on the PCI interface Ordering Rules Compliance Enable (PCI) This bit controls how the AMD-762TM system controller PCI bus interface orders transactions. 0 = PCI ordering rules compliance disabled 1 = PCI ordering rules compliance enabled 9 Clk66Dis1 8 Clk66Dis0 7--6 5 Reserved M66EN 4 3 2 Reserved Reserved PCI_DT_En 1 PCI_OR_En Chapter 2 AMD-762TM System Controller Programmer's Interface 49 Preliminary Information AMD-762TM System Controller Software/BIOS Design Guide 24462D--March 2002 Bit Definitions Bit 0 Name Func1_En PCI Control (Dev0:F0:0x4C) Function Function 1 Enable This bit controls access to device 0, function 1 configuration space (DDR PDL registers). Refer to "Device 0, Function 1: DDR PDL Configuration Registers" on page 106 for more information on the function 1 registers. 0 = Device 0, function 1 disabled 1 = Device 0, function 1 enabled Programming Notes If the target latency bit is set (bit 23 of Dev 0:F0:0x84), then the delayed transactions enable (bit 2) must be set when the front-side bus is clocked at 66 MHz. When enabling PCI ordering rules compliance, it is recommended that delayed transactions be enabled simultaneously for optimal performance. Refer to See Chapter 5, "PCI Bus Interface" on page 203 for more information on the transaction options in the AMD-762 system controller. Refer to See Chapter 7, "Recommended BIOS Settings" on page 219 for the recommended bit settings for these bits. In 66-MHz PCI mode, any unused PCI_66CLK[2:0] signals can be disabled with the Clk66Dis[2:0] bits, but it is imperative that the clock connected to the Southbridge not be disabled. 50 AMD-762TM System Controller Programmer's Interface Chapter 2 Preliminary Information 24462D--March 2002 AMD-762TM System Controller Software/BIOS Design Guide AMD AthlonTM Processor System Bus Dynamic Compensation 31 Bit Reset R/W 23 Bit Reset R/W 15 Bit Reset R/W 7 Bit Reset R/W 0 6 SlewCntl 1 R/W 1 5 4 BYP 0 R/W 0 0 R 0 0 14 BYP_P 0 0 R/W 3 2 Reserved 0 1 0 0 13 12 0 0 22 PVal 0 0 R 11 10 BYP_N 0 9 0 0 21 20 0 0 0 0 R 19 18 NVal 0 30 29 28 Reserved 0 0 0 27 26 Dev0:F0:0x50 25 24 0 17 16 0 8 0 0 0 Register Description Note that the default value of the BYP, BYP_P, and BYP_N fields of this register can be optionally controlled by SIP bits when loading the SIP stream from external ROM.This applies only to the SIP stream for the Boot Strap Processor (P0). This register controls the bypass values for both AMD AthlonTM system bus interfaces in a two-processor system. Chapter 2 AMD-762TM System Controller Programmer's Interface 51 Preliminary Information AMD-762TM System Controller Software/BIOS Design Guide 24462D--March 2002 Bit Definitions Bit 31-24 23-20 Name Reserved Pval Function Reserved AMD AthlonTM System Bus Dynamic Compensation (Dev0:F0:0x50) P Transistor Strength Value This field reflects the P transistor strength value that was automatically written to the AMD AthlonTM processor system bus I/O pads by the auto-compensation circuit. In bypass mode (bit 4=1) this field returns the values in the BYP_P field (bits [15:12]). The P values are active Low. N Transistor Strength Value This field reflects the N transistor strength value that was automatically written to the AMD Athlon processor system bus I/O pads by the auto-compensation circuit. In bypass mode (bit 4=1) this field returns the values in the BYP_N field (bits [11:8]). The N values are active High. Bypass Values P Driver Bypass strength values for the P driver. The P values are active Low. A value of 0 on bit 3 for instance signifies that (2^3 + 1) or 9 legs of the P driver are active. Bypass Values N Driver Bypass strength values for the N driver. The N values are active High. A value of 1 on bit 3, for instance signifies that (2^3 + 1) or 9 legs of the N driver are active. Slew Rate Control Slew rate control for AMD Athlon processor system bus. 000 = Slew rate 0 (slowest) 001 = Slew rate 1 010 = Slew rate 2 011 = Slew rate 3 (default) 100 = Slew rate 4 101= Slew rate 5 110 = Slew rate 6 111 = Slew rate 7 (fastest) 19-16 NVal 15-12 BYP_P 11-8 BYP_N 7-5 SlewCntl 4 BYP Bypass Setting the bypass bit allows an external drive strength setting to be provided in the BYP_P and BYP_N fields. Clearing this bit causes the drive strength to be provided by the compensation circuit. Reserved 3-0 Reserved Programming Notes 52 AMD-762TM System Controller Programmer's Interface Chapter 2 Preliminary Information 24462D--March 2002 AMD-762TM System Controller Software/BIOS Design Guide DRAM Timing 31 Bit Reset R/W 23 Bit Reset R/W 22 21 Reserved 0 0 R 14 PH_Limit X R/W 7 Bit Reset R/W 6 5 X 0 R 4 3 2 13 Reserved 0 X 12 11 10 tRC X R/W 1 X 0 0 X 20 30 29 28 27 26 SBPWaitState AddrTiming_A AddrTiming_B RD_Wait_State Reg_DIMM_En X X X X R/W 19 18 X Dev0:F0:0x54 25 24 tWTR X X tWR X 17 Idle_Cyc_Limit X R/W 9 16 tRRD X R/W 15 X 8 Bit Reset R/W tRP X 0 tRP X X tRAS X X R/W X tCL X X tRCD X Register Description This register defines the DRAM timing parameters for all banks. BIOS software must set appropriate values in this register before setting the SDRAM_Init bit (See "Bit Definitions DRAM Mode/Status (Dev0:F0:0x58)" on page 59) or attempting any DRAM accesses. Note that this register is not initialized at reset time, and all bits must be initialized by BIOS for proper operation. This action should be done prior to attempting DRAM access. Chapter 2 AMD-762TM System Controller Programmer's Interface 53 Preliminary Information AMD-762TM System Controller Software/BIOS Design Guide 24462D--March 2002 Bit Definitions Bit 31 Name SBP_Wait_State Function DRAM Timing (Dev0:F0:0x54) Super Bypass Wait State This bit forces a wait state on all super bypass reads. This bit should be set when the bus speed is 133 MHz (refer to Table 8 on page 57). 0 = No additional wait state on super bypass reads 1 = Add wait state on super bypass reads Address Timing for Copy-A This bit determines whether an extra delay is added to the address and command buses (MAA[14:0], RASA#, CASA#; WEA#, CKEA, CS[5:4, 1:0]#). This bit should be programmed depending on the loading presented to these pins. 0 = No extra delay 1 = XX ps delay Address Timing for Copy-B This bit determines whether an extra delay is added to the address and command buses (MAB[14:0], RASB#, CASB#; WEB#, CKEB, CS[7:6, 3:2]#). This bit should be programmed depending on the loading presented to these pins. 0 = No extra delay 1 = XX ps delay Read Wait State This bit determines whether a wait state must be added before returning the read data from the memory to the requester. This bit should be programmed depending on the overall round-trip timing. Note that this bit must be set for 100-MHz and 133-MHz operation, but it must not be set for 66-MHz operation (refer to Table 8). 0 = No wait states 1 = One wait state Registered DIMM Enable This bit enables the use of registered DIMMs on the motherboard. This bit must be set for normal operation. The AMD-762 system controller supports only registered DIMMs. 0 = Reserved 1 = Registered DIMMs 30 AddrTiming_A 29 AddrTiming_B 28 RD_Wait_State 27 Reg_DIMM_En 26 tWTR Write Data In to Read Command Delay This bit controls the number of clock cycles that must occur between the last valid write operation and the next read command. 0 = tWTR duration is 1 clock cycle. 1 = tWTR duration is 2 clock cycles. 54 AMD-762TM System Controller Programmer's Interface Chapter 2 Preliminary Information 24462D--March 2002 AMD-762TM System Controller Software/BIOS Design Guide Bit Definitions (Continued) Bit 25-24 Name tWR Function DRAM Timing (Dev0:F0:0x54) Write Recovery Time This bit field controls the number of clock cycles that must occur from the last valid write operation to the earliest time a new precharge command can be asserted to the same bank. 00 = tWR duration is 1 clock cycle. 01 = Reserved 10 = tWR duration is 2 clock cycles. 11 = tWR duration is 3 clock cycles. 23 tRRD Activate Bank A to Activate Bank B Command Delay This bit controls the number of clock cycles between successive activate commands to different banks. 0 = tRRD duration is 2 clock cycles. 1 = tRRD duration is 3 clock cycles. Reserved Idle Cycle Limit This bit field controls the number of idle cycles to wait before precharging an idle bank. Idle cycles are defined as cycles in which no valid requests are asserted. 111 = Disable idle precharge 110 = 48 cycles 101 = 32 cycles 100 = 24 cycles 011 = 16 cycles 010 = 12 cycles 001 = 8 cycles (recommended "safe" configuration) 000 = 0 cycles Page Hit Limit This bit field controls the number of consecutive page hit requests to allow before choosing a non-PH request. 00 = 1 cycle 01 = 4 cycle 10 = 8 cycles (recommended "safe" configuration) 11 = 16 cycles Reserved 22-19 18-16 Reserved Idle_Cyc_Limit 15-14 PH_Limit 13-12 Reserved Chapter 2 AMD-762TM System Controller Programmer's Interface 55 Preliminary Information AMD-762TM System Controller Software/BIOS Design Guide 24462D--March 2002 Bit Definitions (Continued) Bit 11-9 Name tRC DRAM Timing (Dev0:F0:0x54) Function tRC This bit field indicates the tRC timing value (bank cycle time: minimum time from activate to activate of same bank). 111 = 10 cycles 110 = 9 cycles 101 = 8 cycles (recommended "safe" configuration) 100 = 7 cycles 011 = 6 cycles 010 = 5 cycles 001 = 4 cycles 000 = 3 cycles tRP This bit field indicates the tRP timing value (precharge time: time from precharge to activate on the same bank). 00 = 3 cycles (recommended "safe" configuration) 01 = 2 cycles 10 = 1 cycles 11 = 4 cycles tRAS This bit field indicates the tRAS timing value (minimum bank active time: time from activate to precharge of same bank). 111 = 9 cycles 110 = 8 cycles 101 = 7 cycles (recommended "safe" configuration) 100 = 6 cycles 011 = 5 cycles 010 = 4 cycles 001 = 3 cycles 000 = 2 cycles CAS Latency of SDRAM 11 = Reserved 10 = 2.5 cycles 01 = 2 cycles (recommended "safe" configuration) 00 = 3 cycles 8-7 tRP 6-4 tRAS 3-2 tCL 56 AMD-762TM System Controller Programmer's Interface Chapter 2 Preliminary Information 24462D--March 2002 AMD-762TM System Controller Software/BIOS Design Guide Bit Definitions (Continued) Bit 1-0 Name tRCD Function DRAM Timing (Dev0:F0:0x54) tRCD This bit field (tRCD) is the timing value (RAS to CAS latency, delay from activate to RD/WR command). 11 = 4 cycles 10 = 3 cycles (recommended "safe" configuration) 01 = 2 cycles 00 = 1 cycle Programming Notes This register is not initialized at reset. BIOS must initialize all bits in this register prior to setting the SDRAM_Init bit (See "Bit Definitions DRAM Mode/Status (Dev0:F0:0x58)" on page 59) or attempting DRAM access for correct operation. The required settings for the wait state bits for SBP_Wait_State and Rd_Wait_State are listed in Table 8. Table 8. Wait State Settings for DRAM Timing Register SBP_Wait_State [Bit 31] 0 0 1 Rd_Wait_State [Bit 28] 0 1 1 DDR Interface Frequency 66 MHz 100 MHz 133 MHz Chapter 2 AMD-762TM System Controller Programmer's Interface 57 Preliminary Information AMD-762TM System Controller Software/BIOS Design Guide 24462D--March 2002 DRAM Mode/Status 31 Bit Reset R/W 23 Bit Reset R/W Mode_Reg _ Status 0 R/W1S 15 Bit Reset R/W 7 Bit Reset R/W 6 5 4 0 0 0 0 R 3 2 1 14 13 12 Reserved 0 0 0 0 22 21 Clk_Dis5 0 30 Clk_Dis4 0 29 Clk_Dis3 0 R/W 20 Burst_Ref_En 0 X 19 Ref_Dis X R/W 11 10 9 18 Reserved X X 28 Clk_Dis2 0 27 Clk_Dis1 0 26 Clk_Dis0 0 Dev0:F0:0x58 25 SDRAM_Init 0 R/W1S 17 24 Reserved 0 R 16 STR_Control Cyc_Per_Ref X 8 0 0 CS7_X4Mode CS6_X4Mode CS5_X4Mode CS4_X4Mode CS3_X4Mode CS2_X4Mode CS1_X4Mode CS0_X4Mode X R/W X R/W X R/W X R/W X R/W X R/W X R/W X R/W Register Description This register provides general mode control and status reporting of the DRAM system. Note that some bits of this register are not initialized at reset time, and all bits must be initialized by BIOS for proper operation. This action should be done prior to attempting DRAM access. 58 AMD-762TM System Controller Programmer's Interface Chapter 2 Preliminary Information 24462D--March 2002 AMD-762TM System Controller Software/BIOS Design Guide Bit Definitions Bit 31 Name Clk_Dis5 Function DRAM Mode/Status (Dev0:F0:0x58) Clock Disable This bit controls the DDR CLKOUT5/CLKOUT5# differential clock pair: 0 = Clock pair enabled 1 = Clock pair disabled (three-stated) Note: This bit is meant to disable the clock pair when it is not connected to anything. This bit should not be used for memory sizing or power management uses. 30 Clk_Dis4 Clock Disable This bit controls the DDR CLKOUT4/CLKOUT4# differential clock pair. 0 = Clock pair enabled 1 = Clock pair disabled (three-stated) Note: This bit is meant to disable the clock pair when it is not connected to anything. This bit should not be used for memory sizing or power management uses. Clock Disable This bit controls the DDR CLKOUT3/CLKOUT3# differential clock pair. 0 = Clock pair enabled 1 = Clock pair disabled (three-stated) Note: This bit is meant to disable the clock pair when it is not connected to anything. This bit should not be used for memory sizing or power management uses. Clock Disable This bit controls the DDR CLKOUT2/CLKOUT2# differential clock pair. 0 = Clock pair enabled 1 = Clock pair disabled (three-stated) Note: This bit is meant to disable the clock pair when it is not connected to anything. This bit should not be used for memory sizing or power management uses. Clock Disable This bit controls the DDR CLKOUT1/CLKOUT1# differential clock pair. 0 = Clock pair enabled 1 = Clock pair disabled (three-stated) Note: This bit is meant to disable the clock pair when it is not connected to anything. This bit should not be used for memory sizing or power management uses. Clock Disable This bit controls the DDR CLKOUT0/CLKOUT0# differential clock pair. 0 = Clock pair enabled 1 = Clock pair disabled (three-stated) Note: This bit is meant to disable the clock pair when it is not connected to anything. This bit should not be used for memory sizing or power management uses. 29 Clk_Dis3 28 Clk_Dis2 27 Clk_Dis1 26 Clk_Dis0 Chapter 2 AMD-762TM System Controller Programmer's Interface 59 Preliminary Information AMD-762TM System Controller Software/BIOS Design Guide 24462D--March 2002 Bit Definitions (Continued) Bit 25 Name SDRAM_Init Function DRAM Mode/Status (Dev0:F0:0x58) SDRAM Initialization This bit is used by the BIOS to tell the SDRAM controller to start the SDRAM initialization sequence. Once set, this bit cannot be reset. The BIOS should first program the SDRAM timing registers and set the output buffer drive strength. After that, it should set this bit. Reserved Mode Register Status 0 = Off/done 1 = Set When clear, the Mode register write is disabled and/or Mode register write done. When set, the Mode register write is enabled. Configuration bits tCL must be set before this bit is asserted. BIOS software sets this bit for write to the SDRAM Mode register. The memory controller clears this bit when it has issued the Mode register write to the SDRAM. 24 23 Reserved Mode_Reg_Status 22-21 STR_Control Suspend to RAM Control These bits are used to allow the BIOS to communicate the power-up sequence to the AMD-762 system controller memory controller and power management logic, as follows: 00 = Default. These bits are cleared to this state any time the RESET# pin is asserted. The AMD-762 memory controller always drives the CKE pins inactive (Low) while these bits are Low. 01 = BIOS sets this pattern after the system resumes from S4 (suspend to disk), S5 (soft off), or mechanical off states. This action causes the AMD-762 memory controller to assert the CKE pins and follow the normal sequence for DDR DRAM initialization after power-on. 1X = BIOS sets this pattern when the system is resuming from the S3 (suspend to RAM) state. This action causes the AMD-762 memory controller to exit self-refresh while preserving all memory data. Burst Refresh Enable 0 = AMD-762 system controller does not burst refreshes. 1 = AMD-762 system controller queues up to four refreshes before issuing. Refreshes are only queued during long sequences of operations to the same memory device. 20 Burst_Ref_En 19 Ref_Dis Refresh Disable This bit is provided for system debug, and should be cleared for normal operation. 0 = Refresh enabled (normal operation) 1 = Refresh disabled (debug only) Reserved 18 Reserved 60 AMD-762TM System Controller Programmer's Interface Chapter 2 Preliminary Information 24462D--March 2002 AMD-762TM System Controller Software/BIOS Design Guide Bit Definitions (Continued) Bit 17--16 Name Cyc_Per_Ref Function DRAM Mode/Status (Dev0:F0:0x58) Cycles Per Refresh Refresh counter defines period of refresh requests. The following table shows the relationship between the values in this field and the resultant refresh period for the different system clock frequencies: Value 00 01 10 11 66 MHz 30.72 s 23.04 s 15.36 s 7.68 s 100 MHz 20.48 s 15.36 s 10.24 s 7.68 s 133 MHz 15.36 s 11.52 s 7.68 s 3.84 s 15-8 7 Reserved CS7_X4Mode Reserved Chip-Select 7 X4Mode Enable 0 = This chip select consists of non-x4 devices (disabled). 1 = This chip select consists of x4 devices (enabled). Chip-Select 6 X4Mode Enable 0 = This chip select consists of non-x4 devices (disabled). 1 = This chip select consists of x4 devices (enabled). Chip-Select 5 X4Mode Enable 0 = This chip select consists of non-x4 devices (disabled). 1 = This chip select consists of x4 devices (enabled). Chip-Select 4 X4Mode Enable 0 = This chip select consists of non-x4 devices (disabled). 1 = This chip select consists of x4 devices (enabled). Chip-Select 3 X4Mode Enable 0 = This chip select consists of non-x4 devices (disabled). 1 = This chip select consists of x4 devices (enabled). Chip-Select 2 X4Mode Enable 0 = This chip select consists of non-x4 devices (disabled). 1 = This chip select consists of x4 devices (enabled). Chip-Select 1 X4Mode Enable 0 = This chip select consists of non-x4 devices (disabled). 1 = This chip select consists of x4 devices (enabled). Chip-Select 0 X4Mode Enable 0 = This chip select consists of non-x4 devices (disabled). 1 = This chip select consists of x4 devices (enabled). 6 CS6_X4Mode 5 CS5_X4Mode 4 CS4_X4Mode 3 CS3_X4Mode 2 CS2_X4Mode 1 CS1_X4Mode 0 CS0_X4Mode Chapter 2 AMD-762TM System Controller Programmer's Interface 61 Preliminary Information AMD-762TM System Controller Software/BIOS Design Guide 24462D--March 2002 Programming Notes Note that some bits of this register are not initialized at reset time, and all bits must be initialized by BIOS for proper operation. This action should be done prior to attempting DRAM access. The Clk_Dis bits are cleared by RESET#, and therefore all DDR DRAM interface clock pairs are enabled when exiting the Advanced Configuration and Power Interface (ACPI) S3 sleep state (suspend to RAM). BIOS should disable any clock pairs that are connected to unpopulated DIMM slots upon exit of S3. When a chip select is programmed to operate in x4 DIMM mode, the DM[8:0] pins become DQS pins for that chip select. The pad configuration for the DM[8:0] pins is automatically controlled by the DQS_Drive field (Dev 0:F0:0x40) instead of the MDAT_Drive field, when any chip select is configured for x4 DIMM mode. 62 AMD-762TM System Controller Programmer's Interface Chapter 2 Preliminary Information 24462D--March 2002 AMD-762TM System Controller Software/BIOS Design Guide BIU0 Status/Control 31 Bit Reset R/W 23 Bit Reset R/W 15 Bit Reset R/W 7 Bit Reset R/W SysDC_Out _Dly 0 R/W 6 5 4 Prb_Limit 0 0 0 R 3 2 WR2_RD Pinstrapping R 14 13 12 Ack_Limit 1 1 0 22 21 20 Xca_WR_Cnt 0 0 0 R/W 11 10 9 0 Prb_En 0 30 Reserved 0 29 Reserved 0 28 Reserved 0 R/W 19 18 Reserved 0 0 27 26 Xca_Prb_Cnt 0 0 Dev0:F0:0x60 25 24 Xca_RD_Cnt 0 17 Stp_Grant _Discon_En 0 16 Prb_Limit 0 Xca_RD_Cnt 8 SysDC_Out _Dly Pinstrapping R 0 RD2_WR Bypass_En 0 R/W 1 SysDC_In_Dly Register Description This register provides general status and control for the AMD AthlonTM processor system bus interface for processor 0. Chapter 2 AMD-762TM System Controller Programmer's Interface 63 Preliminary Information AMD-762TM System Controller Software/BIOS Design Guide 24462D--March 2002 Bit Definitions Bit Name 31 Prb_En BIU0 Status/Control (Dev0:F0:0x60) Function Probe Enable 0 = Probes are not sent to this processor. 1 = Probes are sent to this processor. This bit must be programmed to zero for normal operation. This bit must be programmed to zero for normal operation. This bit must be programmed to zero for normal operation. Xca Probe Count This bit field represents the maximum number of consecutive AMD AthlonTM processor system bus grants for probe data movement types that are allowed before letting another type have the bus. The recommended value to be loaded in this field by BIOS software is 0x2. A value of 0x0 is treated identically to 0x1. Xca Read Count This bit field represents the maximum number of consecutive AMD Athlon processor system bus grants for read data movement types that are allowed before letting another type have the bus. The recommended value to be loaded in this field by BIOS software is 0x6. A value of 0x0 is treated identically to 0x1. Xca Write Count This bit field represents the maximum number of consecutive AMD Athlon processor system bus grants for write data movement types that are allowed before letting another type have the bus. The recommended value to be loaded in this field by BIOS software is 0x6. A value of 0x0 is treated identically to 0x1. Reserved Stop Grant Disconnect Enable 0 = No AMD Athlon processor system bus disconnect is performed following STOP/GRANT. 1 = AMD Athlon processor system bus disconnects after receiving a STOP/GRANT special cycle. Probe Limit BIOS software initializes this field with the maximum number of outstanding probes that the given CPU can handle. The default is a single probe. Encoding is as follows: 0b000 = 1 probe 0b001 = 2 probes ................................ 0b111 = 8 probes Ack Limit BIOS software reads this field to determine how many outstanding unacknowledged AMD Athlon processor system bus commands can be sent to the AMD-762TM system controller. The AMD-762 system controller allows a maximum of four unacknowledged commands. Encoding is as follows: 0b0000 = 1 unacknowledged command 0b0001 = 2 unacknowledged commands .......................................................... 0b1111 = 16 unacknowledged commands 30 29 28 27-25 Reserved Reserved Reserved Xca_Prb_Cnt 24-22 Xca_RD_Cnt 21-19 Xca_WR_Cnt 18 17 Reserved Stp_Grant_ Discon_En Prb_Limit 16-14 13-10 Ack_Limit 64 AMD-762TM System Controller Programmer's Interface Chapter 2 Preliminary Information 24462D--March 2002 AMD-762TM System Controller Software/BIOS Design Guide Bit Definitions (Continued) BIU0 Status/Control (Dev0:F0:0x60) Bit Name Function 9 Bypass_En Bypass Enable When set, the AMD-762TM system controller internally bypasses certain memory pipe stages for optimal performance. This bit may be set only if both of the following are true: 1. System is single processor or it is two processors and only CPU0 is present, and 2. CPU clock multiplier is 4 or greater. See "Config Status" on page 82 to determine the clock multiplier (FID). 8-7 SysDC_Out_Dly SysDC Out Delay This bit field specifies the number of SysClk cycles from a return of read data type SysDC command and the start of the corresponding data. 0b00 = Reserved 0b01 = 1 clock 0b10 = 2 clocks 0b11 = 3 clocks 6-3 SysDC_In_Dly This field is initialized by pinstrapping during reset. SysDC In Delay This bit field specifies the number of SysClk cycles from a write data type SysDC command and the start of the corresponding data. 0b0000 = 1 clock 0b0001 = 2 clocks ............................. 0b1111 = 16 clocks 2 WR2_RD This field is initialized by pinstrapping during reset. WR2 Read This field defines the number of SysClk cycles that are inserted between write data and read data cycles to allow the AMD AthlonTM processor system bus data wires to turn around. This field is initialized by pinstrapping during reset. RD2 Write This field defines the number of SysClk cycles that are inserted between read data and write data cycles to allow the AMD Athlon processor system bus data wires to turn around. This field is initialized by pinstrapping during reset. 1-0 RD2_WR Programming Notes Chapter 2 AMD-762TM System Controller Programmer's Interface 65 Preliminary Information AMD-762TM System Controller Software/BIOS Design Guide 24462D--March 2002 BIU0 SIP 31 Bit Reset R/W Clk_Fwd_Offset 0 R/W 23 Bit Reset R/W 15 Bit Reset R/W 7 Bit Reset R/W 6 5 4 Sys_Data_Rec_Mux_PreLd Pinstrapping R Sys_Addr_Dly 14 13 SysDC_Dly Pinstrapping R 3 2 1 12 22 Sys_Data_Odd_Clk_Dly 21 20 30 29 28 27 26 Data_Init_Cnt Addr_Init_Cnt Pinstrapping R 19 18 Dev0:F0:0x64 25 Sys_Data_Even_Clk_Dly 24 17 16 Sys_Addr_Dly Sys_Data_Even_Dly Pinstrapping R 11 Sys_Data_Odd_Dly 10 9 Sys_Addr_Clk_Dly 8 0 Sys_Rst_Clk_Offset 0 0 Sys_Addr_Rec_Mux_PreLd Register Description This register provides visibility to the serial initialization packet delivered to the AMD AthlonTM processor during the AMD Athlon processor system bus connect protocol. 66 AMD-762TM System Controller Programmer's Interface Chapter 2 Preliminary Information 24462D--March 2002 AMD-762TM System Controller Software/BIOS Design Guide Bit Definitions Bit Name 31 Clk_Fwd_Offset BIU0 SIP (Dev0:F0:0x64) Function Clock Forward Offset 0 = The AMD-762TM system controller delays driving of the data and clock for AMD AthlonTM processor system bus SysData bits [31:16] and [63:48] by ~1000 ps. 1 = All AMD Athlon system bus ClkFWD groups drive the same nominally SysClk edge. Data Initialization Count This value specifies the number of SysClks from the launch of data by the processor until it can be read from the AMD-762 system controller receive FIFO. Address Initialization Count This value specifies the number of SysClks from the launch of a command by the processor until it can be read from the AMD-762 system controller receive FIFO. System Data Even Clock Delay -- AMD Athlon processor SIP[33:31] This value specifies the number of processor XICLK phases between the nominal start of bit time and the launch of the even clocks. System Data Odd Clock Delay -- AMD Athlon processor SIP[30:28] This value specifies the number of processor XICLK phases between the nominal start of bit time and the launch of the odd clocks. System Data Even Delay -- AMD Athlon processor SIP[27:26] This value specifies the number of processor XICLK phases between the nominal start of bit time and the launch of the even data (SysData bits [31:16] and [63:48]). System Data Odd Delay -- AMD Athlon processor SIP[25:24] This value specifies the number of processor XICLK phases between the nominal start of bit time and the launch of the odd data (SData bits [15:00] and [47:32]). System Address Delay -- AMD Athlon processor SIP[23:22] This value specifies the number of processor XICLK phases between the nominal start of bit time and the launch of the address (SysAddOut). SysDC Delay -- AMD Athlon processor SIP[19:16] This value is an internal processor parameter that is used to cause SYSDC commands and their associated data to arrive in the processor core at the correct relative times. System Addr Clock Delay-- AMD Athlon processor SIP[13:11] This value specifies the number of processor XICLK phases between the nominal start of bit time and the launch of the SADDOUTCLK. System Reset Clock Offset -- AMD Athlon processor SIP[10:9] This value is an internal processor parameter that is used to properly time AMD Athlon system bus data transfer. System Data Rec Mux PreLd -- AMD Athlon processor SIP[8:6] This value specifies the number of SysClk phases from the launch of data by the AMD-762 system controller until it can be read from the AMD Athlon receive FIFO. System Address Rec Mux PreLd -- AMD Athlon processor SIP[5:3] This value specifies the number of SysClk phases from the launch of address/command by the AMD-762 system controller until it can be read from the AMD Athlon receive FIFO. 30-29 Data_Init_Cnt 28-27 Addr_Init_Cnt 26-24 Sys_Data_Even _Clk_Dly Sys_Data_Odd _Clk_Dly Sys_Data_Even _Dly Sys_Data_Odd _Dly Sys_Addr_Dly 23-21 20-19 18-17 16-15 14-11 SysDC_Dly 10-8 Sys_Addr_Clk _Dly Sys_Rst_Clk _Offset Sys_Data_Rec _Mux_PreLd Sys_Addr_Rec _Mux_PreLd 7-6 5-3 2-0 Programming Notes Chapter 2 AMD-762TM System Controller Programmer's Interface 67 Preliminary Information AMD-762TM System Controller Software/BIOS Design Guide 24462D--March 2002 BIU1 Status/Control 31 Bit Reset R/W 23 Bit Reset R/W 15 Bit Reset R/W 7 Bit Reset R/W SysDC_Out _Dly 0 R/W 6 5 4 Prb_Limit 0 0 0 14 13 12 Ack_Limit 1 R 3 2 WR2_RD Pinstrapping R 1 1 0 22 21 20 Xca_WR_Cnt 0 0 0 R/W 11 10 9 0 Prb_En 0 30 Reserved 0 29 Reserved 0 28 Reserved 0 R/W 19 18 Reserved 0 0 27 26 Xca_Prb_Cnt 0 0 Dev0:F0:0x68 25 24 Xca_RD_Cnt 0 17 Stp_Grant _Discon_En 0 16 Prb_Limit 0 Xca_RD_Cnt 8 SysDC_Out _Dly Pinstrapping R 0 RD2_WR Reserved 0 SysDC_In_Dly Register Description This register provides general status and control for the AMD AthlonTM processor system bus interface for processor 1. 68 AMD-762TM System Controller Programmer's Interface Chapter 2 Preliminary Information 24462D--March 2002 AMD-762TM System Controller Software/BIOS Design Guide Bit Definitions Bit Name 31 Prb_En BIU1 Status/Control (Dev0:F0:0x68) Function Probe Enable 0 = Probes not sent to this processor 1 = Probes sent to this processor This bit must be programmed to zero for normal operation. This bit must be programmed to zero for normal operation. This bit must be programmed to zero for normal operation. Xca Probe Count This bit field represents the maximum number of consecutive AMD AthlonTM processor system bus grants for probe data movement types that are allowed before letting another type have the bus. The recommended value to be loaded in this field by BIOS software is 0x2. A value of 0x0 is treated identically to 0x1. Xca Read Count This bit field represents the maximum number of consecutive AMD AthlonTM processor system bus grants for read data movement types that are allowed before letting another type have the bus. The recommended value to be loaded in this field by BIOS software is 0x6. A value of 0x0 is treated identically to 0x1. Xca Write Count This bit field represents the maximum number of consecutive AMD AthlonTM processor system bus grants for write data movement types that are allowed before letting another type have the bus. The recommended value to be loaded in this field by BIOS software is 0x6. A value of 0x0 is treated identically to 0x1. Reserved Stop Grant Disconnect Enable 0 = No AMD AthlonTM processor system bus disconnect performed following STOP/GRANT. 1 = BIU performs an AMD AthlonTM processor system bus disconnect after receiving a STOP/GRANT special cycle. Probe Limit BIOS software initializes this field with the maximum number of outstanding probes that the given CPU can handle. The default is a single probe. Encoding is as follows: 0b000 = 1 probe 0b001 = 2 probes ................................ 0b111 = 8 probes Ack Limit BIOS software reads this field to determine how many outstanding unacknowledged AMD AthlonTM processor system bus commands can be sent to the AMD-762TM system controller. Encoding is as follows: 0b0000 = 1 unacknowledged commands 0b0001 = 2 unacknowledged commands .......................................................... 0b1111 = 16 unacknowledged commands Reserved 30 29 28 27-25 Reserved Reserved Reserved Xca_Probe_Cnt 24-22 Xca_RD_Cnt 21-19 Xca_WR_Cnt 18 17 Reserved Stp_Grant_ Discon_En 16-14 Prb_Limit 13-10 Ack_Limit 9 Reserved Chapter 2 AMD-762TM System Controller Programmer's Interface 69 Preliminary Information AMD-762TM System Controller Software/BIOS Design Guide 24462D--March 2002 Bit Definitions (Continued) BIU1 Status/Control (Dev0:F0:0x68) Bit Name Function 8-7 SysDC_Out_Dly SysDC Out Delay This field specifies the number of SysClk cycles from a return read data type AMD AthlonTM processor system bus SysDC and the start of the corresponding data. 0b00 = Reserved 0b01 = 1 Clks 0b10 = 2 Clks 0b11 = 3 Clks 6-3 SysDC_In_Dly This field is initialized by pinstrapping during reset. SysDC In Delay This field specifies the number of SysClk cycles from a write data type SysDC command and the start of the corresponding data. 0b0000 = 1 clock 0b0001 = 2 clocks ............................. 0b1111 = 16 clocks 2 WR2_RD This field is initialized by pinstrapping during reset. WR2 Read This field defines the number of SysClk cycles that are inserted between Write and Read cycles to allow the AMD AthlonTM processor system bus data wires to turn around. This field is initialized by pinstrapping during reset. RD2 Write This field defines the number of SysClk cycles that are inserted between Read and Write cycles to allow the AMD Athlon system bus data wires to turn around. This field is initialized by pinstrapping during reset. 1-0 RD2_WR Programming Note 70 AMD-762TM System Controller Programmer's Interface Chapter 2 Preliminary Information 24462D--March 2002 AMD-762TM System Controller Software/BIOS Design Guide BIU1 SIP 31 Bit Reset R/W Clk_Fwd_Offset 0 R/W 23 Bit Reset R/W 15 Bit Reset R/W 7 Bit Reset R/W 6 5 4 Sys_Data_Rec_Mux_PreLd Pinstrapping R Sys_Addr_Dly 14 13 SysDC_Dly Pinstrapping R 3 2 1 12 22 Sys_Data_Odd_Clk_Dly 21 20 30 29 28 27 26 Data_Init_Cnt Addr_Init_Cnt Pinstrapping R 19 18 Dev0:F0:0x6C 25 Sys_Data_Even_Clk_Dly 24 17 16 Sys_Addr_Dly Sys_Data_Even_Dly Pinstrapping R 11 Sys_Data_Odd_Dly 10 9 Sys_Addr_Clk_Dly 8 0 Sys_Rst_Clk_Offset 0 0 Sys_Addr_Rec_Mux_PreLd Register Description This register provides visibility to the Serial Initialization packet delivered to the AMD Athlon processor during the AMD AthlonTM processor system bus connect protocol. Chapter 2 AMD-762TM System Controller Programmer's Interface 71 Preliminary Information AMD-762TM System Controller Software/BIOS Design Guide 24462D--March 2002 Bit Definitions Bit 31 Name Clk_Fwd_Offset Function BIU1 SIP (Dev0:F0:0x6C) Clock Forward Offset 0 = The AMD-762TM system controller delays driving of the data and clock for AMD AthlonTM processor system bus SysData bits [31:16] and [63:48] by ~1000 ps. 1 = All AMD Athlon processor system bus ClkFWD groups drive the same nominally SysClk edge. 30-29 Data_Init_Cnt Data Initialization Count This value specifies the number of SysClks from the launch of data by the processor until it can be read from the AMD-762 system controller receive FIFO. Address Initialization Count This value specifies the number of SysClks from the launch of a command by the processor until it can be read from the AMD-762 system controller receive FIFO. System Data Even Clock Delay -- AMD Athlon processor SIP[33:31]. This value specifies the number of processor XICLK phases between the nominal start of bit time and the launch of the even clocks. System Data Odd Clock Delay -- AMD Athlon processor SIP[30:28]. This value specifies the number of processor XICLK phases between the nominal start of bit time and the launch of the odd clocks. System Data Even Delay -- AMD Athlon processor SIP[27:26]. This value specifies the number of processor XICLK phases between the nominal start of bit time and the launch of the even data (SysData bits [31:16] and [63:48]) System Data Odd Delay -- AMD Athlon processor SIP[25:24]. This value specifies the number of processor XICLK phases between the nominal start of bit time and the launch of the odd data (SData bits [15:00] and [47:32]). System Address Delay -- AMD Athlon processor SIP[23:22]. This value specifies the number of processor XICLK phases between the nominal start of bit time and the launch of the address (SysAddOut). SysDC Delay -- AMD Athlon processor SIP[19:16]. This is an internal processor parameter that is used to cause SYSDC commands and their associated data to arrive in the processor core at the correct relative times. System Addr Clock Delay -- AMD Athlon processor SIP[13:11]. This value specifies the number of processor XICLK phases between the nominal start of bit time and the launch of the SADDOUTCLK. System Reset Clock Offset -- AMD Athlon processor SIP[10:9]. This value is an internal processor parameter that is used to properly time AMD Athlon processor system bus data transfer. 28-27 Addr_Init_Cnt 26-24 Sys_Data_Even _Clk_Dly Sys_Data_Odd _Clk_Dly Sys_Data_Even _Dly Sys_Data_Odd _Dly Sys_Addr_Dly 23-21 20-19 18-17 16-15 14-11 SysDC_Dly 10-8 Sys_Addr_Clk _Dly Sys_Rst_Clk _Offset 7-6 72 AMD-762TM System Controller Programmer's Interface Chapter 2 Preliminary Information 24462D--March 2002 AMD-762TM System Controller Software/BIOS Design Guide Bit Definitions (Continued) Bit 5-3 Name Sys_Data_Rec _Mux_PreLd Sys_Addr_Rec _Mux_PreLd Function BIU1 SIP (Dev0:F0:0x6C) System Data Rec Mux PreLd -- AMD AthlonTM processor SIP[8:6]. This value specifies the number of SysClk phases from the launch of data by the AMD-762TM system controller until it can be read from the AMD Athlon processor receive FIFO. System Address Rec Mux PreLd -- AMD Athlon processor SIP[5:3]. This value specifies the number of SysClk phases from the launch of address/command by the AMD-762 system controller until it can be read from the AMD Athlon processor receive FIFO. 2-0 Programming Notes Chapter 2 AMD-762TM System Controller Programmer's Interface 73 Preliminary Information AMD-762TM System Controller Software/BIOS Design Guide 24462D--March 2002 Memory Status/Control 31 Bit Reset R/W 23 Bit Reset R/W 15 Bit Reset R/W 7 Bit Reset R/W 0 Reserved 0 14 Reserved 0 R/W 6 Reserved 0 R 0 0 0 R 0 0 5 4 0 0 22 21 Reserved 0 R 13 Reserved 0 0 R 3 2 12 Reserved 0 11 10 PCI_Pipe_En 0 R/W 1 0 0 20 0 0 0 0 R 19 18 Self_Ref_En X 30 29 28 Reserved 0 0 0 27 26 Dev0:F0:0x70 25 24 0 17 Reserved 0 R/W 9 PCI_Blk_WR _En 0 16 Reserved 0 8 Reserved 0 R 0 Reserved 0 R Register Description This register provides general status and control for the memory controller. Note that the Self_Ref_En bit in this register is not initialized at reset time, but must be initialized by BIOS for proper operation. This action should be done prior to attempting DRAM access. 74 AMD-762TM System Controller Programmer's Interface Chapter 2 Preliminary Information 24462D--March 2002 AMD-762TM System Controller Software/BIOS Design Guide Bit Definitions Bit Name 31-19 Reserved 18 Self_Ref_En Memory Status/Control (Dev0:F0:0x70) Function Reserved Self-Refresh Enable This bit enables self-refresh when entering certain power management states. This bit should normally be set, but the option to disable this function is provided to accommodate specific DIMMs that do not correctly support the self-refresh feature. Note that if this bit is not set, then DCSTOP# assertion (ACPI sleep states) must be inhibited. 0 = Self-refresh disabled 1 = Self-refresh enabled Reserved Reserved Reserved PCI Pipe Enable 0 = All PCI transactions, from either the PCI or AGP interfaces, force the memory controller to check for outstanding read probes with a matching block address and stall until these probes are complete. 1 = Memory controller pipelines PCI transactions. Setting this bit generally increases PCI throughput. This bit must be clear when the processor is allowed to issue CleanVictimBlock commands. PCI Block Write Enable 0 = PCI full-block writes do RID/INV probes, forcing the memory controller to wait for probe data movement. 1 = PCI full-block writes do NOP/INV probes. This bit must be clear when the AMD AthlonTM processor is allowed to issue CleanVictimBlock commands. Reserved Reserved 17-14 13 12-11 10 Reserved Reserved Reserved PCI_Pipe_En 9 PCI_Blk_WR_En 8-1 0 Reserved Reserved Programming Notes Note that the Self_Ref_En bit in this register is not initialized at reset time but must be initialized by BIOS for proper operation. This action should be done prior to attempting DRAM access. DCSTOP# assertion (ACPI S1/S3) must not be enabled if the Self_Ref_En bit is cleared. Chapter 2 AMD-762TM System Controller Programmer's Interface 75 Preliminary Information AMD-762TM System Controller Software/BIOS Design Guide 24462D--March 2002 Who Am I (WHAMI) 31 Bit Reset R/W 23 Bit Reset R/W 15 Bit Reset R/W 7 Bit Reset R/W 6 5 4 WHAMI CPUID R 0 0 0 0 R 3 2 1 14 13 0 0 22 Reserved 0 R 12 FirstBusID 0 0 0 11 10 9 0 21 20 0 0 0 0 R 19 18 30 29 28 Reserved 0 0 0 27 26 Dev0:F0:0x80 25 24 0 17 16 IReadWHAMI1 IReadWHAMI0 BIU1_Present BIU0_Present 0 0 From CPU From CPU 8 0 0 Register Description Certain software functions, System Management Interrupt for example, can only be executed by one processor. This register allows BIOS software to determine which of the two processors is currently executing the BIOS code. The BIOS might also use the WHAMI value to select the Boot Strap Processor, select the value for the Local APIC ID register, or set the APIC Boot Strap Processor (BSP) indicator bit if his returned AMD Athlon system bus number matches the returned "First BusID". The WHAMI register returns a unique BusID identifying the processor reading the register as well as the BusID of the first processor to read the register after reset. The CPU0 BusID is 0 and the CPU1 BusID is 1. Bits 16 and 17 are "1" if a processor is installed on BIU0 and BIU1, respectively. 76 AMD-762TM System Controller Programmer's Interface Chapter 2 Preliminary Information 24462D--March 2002 AMD-762TM System Controller Software/BIOS Design Guide Bit Definitions Bit 31-20 19 Name Reserved IReadWHAMI1 Function Reserved Who Am I (WHAMI) (Dev0:F0:0x80) I Read WHAMI (Processor 1) This bit is set when the processor connected to the P1 interface reads this register. This bit then remains set until the next reset (RESET# pin is asserted). This bit can be used by the multi-processor BIOS to determine when it is safe to continue access of configuration space. I Read WHAMI (Processor 0) This bit is set when the processor connected to the P0 interface reads this register. This bit then remains set until the next reset (RESET# pin is asserted). This bit can be used by the multi-processor BIOS to determine when it is safe to continue access of configuration space. BIU1 Present This bit, when set, indicates that a processor is installed on the specified AMD AthlonTM processor system bus port on the AMD-762TM system controller and it has requested a Connect sequence (ProcRdy Assertion). BIU0 Present This bit, when set, indicates that a processor is installed on the specified AMD AthlonTM processor system bus port on the AMD-762 system controller and it has requested a connect sequence (ProcRdy assertion). First BusID This field contains the AMD Athlon processor system bus ID of the first processor to read this register: 00h if CPU0 was the first to read WHAMI after reset, 01h if CPU1 was the first to read WHAMI after reset. Who Am I This field returns the AMD Athlon processor system bus ID (below) of the processor that accesses it: 00h for CPU0, 01h for CPU1. 18 IReadWHAMI0 17 BIU1_Present 16 BIU0_Present 15-8 FirstBusID 7-0 WHAMI Programming Notes Chapter 2 AMD-762TM System Controller Programmer's Interface 77 Preliminary Information AMD-762TM System Controller Software/BIOS Design Guide 24462D--March 2002 PCI Arbitration Control 31 Bit Reset R/W 23 Bit Reset R/W Tgt_Latency 0 R/W 15 Bit Reset R/W 7 Bit Reset R/W PM_Reg_En 0 6 15M_Hole 0 5 14M_Hole 0 4 EV6_Mode 0 R/W MDA_Debug 0 14 13 0 0 R 12 11 22 21 Reserved 0 0 20 0 0 0 30 29 28 27 26 AGP_VGA_BIOS 0 R/W 19 18 Reserved 0 R/w 10 0 0 0 Dev0:F0:0x84 25 24 0 17 16 AGP_Chain_En PCI_Chain_En 0 R/W 9 0 R/W 8 PCI_WR_Post AGP_WR_Post RD_Data_Err AGP_Erly_Prb PCI_Erly_Prb AGP_Arb_Pipe SB_Lock_Dis _Rtry _Rtry _Dis _Dis _Dis _Dis 0 0 0 R/W 3 2 1 0 Park_PCI 0 0 0 0 0 Tgt_Lat_Tim AGP_Pref_En PCI_Pref_En _Dis 0 0 0 Register Description This register provides general PCI arbiter mode control. 78 AMD-762TM System Controller Programmer's Interface Chapter 2 Preliminary Information 24462D--March 2002 AMD-762TM System Controller Software/BIOS Design Guide Bit Definitions Bit 31-24 Name AGP_VGA_BIOS Function PCI Arbitration Control (Dev0:F0:0x84) AGP VGA BIOS These bits when set indicate that the corresponding (16-KByte) segment should be mapped to the AGP PCI bus. Bit 24 corresponds to the addresses 0xC0000-0xC3FFF and bit 31 maps addresses 0xDC000-0xDFFFF to the AGP PCI interface. Set one or more of these bits if the AGP graphics card has a ROM BIOS. Target Latency This bit is designed to ensure that the AMD-762TM system controller is compliant to the PCI maximum target latency rule. Note that this compliance applies only to the PCI bus and not the AGP bus. 0 = AMD-751TM system controller-compatible, the AMD-762 system controller does not disconnect a master when it cannot service a read request within 32 PCI clock periods (initial latency) or 8 clocks (subsequent data cycles). 1 = If the AMD-762 system controller cannot respond to a memory read within 32 clocks for the initial access, or 8 clocks for each subsequent access, it forces a retry. Note: To prevent potential deadlocks, set this bit and clear bit 3 (Tgt_Lat_Tim_Dis) if the system has PCI to AGP traffic. 23 Tgt_Latency 22-19 18 17 16 15 Reserved Reserved AGP_Chain_En PCI_Chain_En MDA_Debug Reserved Reserved Enable AGP Chaining When set, CPU writes to the AGP bus are chained together. Enable PCI Chaining When set, CPU writes to PCI are chained together. MDA Debug This bit allows monochrome display adapters (MDA) to be used simultaneously with AGP cards for debug of AGP device drivers. The behavior of the AMD-762TM system controller display adapters is a function of this bit and the VGA Enable in (D1:0x3C[19]) as follows: MDA address ranges: Memory: 0B0000h-0B7FFFh I/O: 3B4h, 3B5h, 3B8h, 3B9h, 3BAh, 3BFh VGA = 0, MDA = 0: all MDA and VGA references go to PCI VGA = 0, MDA = 1: operation undefined VGA = 1, MDA = 0: all VGA references go to AGP, MDA only (I/O 3BFh) goes to PCI VGA = 1, MDA = 1: all VGA references go to AGP, all MDA (including memory) go to PCI 14 13 PCI_WR_Post _Rtry AGP_WR_Post _Rtry PCI Write Post Retry When set, this bit enables retries on PCI if there are pending posted writes. AGP Write Post Retry When set, this bit enables retries on the AGP bus if there are pending posted writes. Chapter 2 AMD-762TM System Controller Programmer's Interface 79 Preliminary Information AMD-762TM System Controller Software/BIOS Design Guide 24462D--March 2002 Bit Definitions (Continued) Bit 12 Name RD_Data_Err_ Dis Function PCI Arbitration Control (Dev0:F0:0x84) Read Data Error Disable Whenever a cycle from a processor to the PCI or AGP buses results in a master abort (except special cycles), the AMD-762 system controller returns a read data error indicator to the processor. When set, this bit causes data value of all 1s to be returned. When clear, an AMD AthlonTM processor system bus read data error response is returned. The CPU response to read data error is determined by the settings of the Machine Check Architecture registers in the processor. AGP Early Probe Disable As soon as the AMD-762 system controller detects a PCI write cycle to memory from an external AGP master, it sends a "probe only" request to the processor that is used to flush data from the processor cache. After one or more data phases, a write request is sent to the memory, which also results in a probe. When set, this bit disables the early probe from an AGP master running a PCI write cycle to memory. PCI Early Probe Disable This bit is similar AGP_Erly_Prb_Dis and can disable early probe requests for write cycles from an external master on the standard PCI bus. AGP Arbiter Pipe Disable When set, this bit disables the AGP arbiter from pipelining grants onto the bus. Southbridge Lock Disable When the Southbridge makes a request for the PCI bus, the AMD-762 system controller makes sure that all the previous posted requests from the processors and PCI are completed by the memory before granting the bus to the Southbridge. When set, this bit disables this flushing of previous requests. Power Management Register Enable This bit, when set, enables reading from and writing to the power management register (at BAR2). 15M Memory Hole When set, this bit creates a hole in memory from 15 Mbytes to 16 Mbytes. This register is used by the PCI decode logic to know when to accept a cycle from an external PCI master. When set, the PCI decode logic does not assert a match for addresses falling in this range. 14M Memory Hole When set, this bit creates a hole in memory from 14 Mbytes to 15 Mbytes. This register is used by the PCI decode logic to know when to accept a cycle from an external PCI master. When set, the PCI decode logic does not assert a match for addresses falling in this range. EV6 Mode When set, this bit indicates that the PCI interfaces have to decode memory hits in the EV6 mode. There are no memory holes and DMA can be done to any address that lies within the SDRAM map. 11 AGP_Erly_Prb_ Dis 10 PCI_Erly_Prb_ Dis AGP_Arb_Pipe_ Dis SB_Lock_Dis 9 8 7 PM_Reg_En 6 15M_Hole 5 14M_Hole 4 EV6_Mode 80 AMD-762TM System Controller Programmer's Interface Chapter 2 Preliminary Information 24462D--March 2002 AMD-762TM System Controller Software/BIOS Design Guide Bit Definitions (Continued) Bit 3 Name Tgt_Lat_Tim_ Dis Function PCI Arbitration Control (Dev0:F0:0x84) Target Latency Timer Disable When the AMD-762 system controller acts as a PCI target, it has a latency timer that retries the (write) cycle if it cannot respond within 8 bus clocks (16 clocks for the first transfer). When set, this bit disables the AMD-762 system controller's target latency timer on both the standard PCI and AGP PCI interfaces. Note: To prevent potential deadlocks caused by PCI to AGP traffic on the system, this bit should be cleared and bit 23 (Tgt_Latency) must be set. Note also that setting this bit disables the Tgt_Latency function controlled by bit 23. AGP Prefetch Enable When set, this bit enables the AMD-762 system controller to prefetch data from the SDRAM when a PCI master on the standard AGP bus reads from the main memory. PCI Prefetch Enable When set, this bit enables the AMD-762 system controller to prefetch data from the SDRAM when a PCI master on the PCI bus reads from the main memory. Park PCI When set, this bit enables parking on an external PCI master. When clear, the PCI arbiter only parks on processor accesses to PCI. 2 AGP_Pref_En 1 PCI_Pref_En 0 Park_PCI Programming Notes To avoid potential deadlocks for systems that use traffic from the PCI bus to the PCI bus of the AGP, clear the write target latency timer disable bit (bit 3, Tgt_Lat_Tim_Dis), and set the read target latency timer bit (bit 23, Tgt_Latency). Refer to the programming notes for the PCI Control register (Dev 0:F0:0x4C) for details on the recommended setting of the Tgt_Latency bit. Chapter 2 AMD-762TM System Controller Programmer's Interface 81 Preliminary Information AMD-762TM System Controller Software/BIOS Design Guide 24462D--March 2002 Config Status 31 Bit Reset R/W 23 Bit Reset R/W 15 Bit Reset R/W 7 Bit Reset R/W SIP_ROM_En x (from ROM_SCK) 6 66MHzPCI x (from PCI AD[15]) 5 In_Clk_En x (from PCI AD[24]) 4 Out_Clk_En x (from PCI AD[8]) R Tristate_En x (from PCI AD[25]) 14 NAND_En x (from PCI AD[23]) 13 12 K7_PP_En x (from PCI C/BE[3]#) 22 IG_PP_En x (from PCI C/BE[2]#) 21 Clk_Speed x (from PCI AD[31:30]) R 11 10 9 20 30 AGP_Clk_Mux x (from PCI AD[14:12]) 29 28 27 Sys_Clk_Mux x (from PCI AD[7:5]) R 19 18 26 Dev0:F0:0x88 25 Type_Det x (from PCI AD[20]) 24 S2K_Thresh x (from PCI AD[4]) 17 16 S2K1_Bus_Len x (from PCI AD[27:26]) S2K0_Bus_Len x (from PCI AD[11:10]) 8 Bypass_PLLs Dis_Divider x (from PCI AD[9]) x (from PCI AD[29]) R 3 CPU1_Divider x (from PCI AD[19:16]) 2 1 0 CPU0_Divider x (from PCI AD[3:0]) Register Description This register allows BIOS software to determine what system initialization states have been programmed by resistor pinstrappings on the motherboard. 82 AMD-762TM System Controller Programmer's Interface Chapter 2 Preliminary Information 24462D--March 2002 AMD-762TM System Controller Software/BIOS Design Guide Bit Definitions Bit 31-29 28-26 25 Name AGP_Clk_Mux Sys_Clk_Mux Type_Det Function AGP Clock Mux For internal test only. System Clock Mux For internal test only. Config Status (Dev0:F0:0x88) Type Detect 0 = This installed card in the AGP slot uses 1.5-V signalling. 1 = This installed card in the AGP slot uses 3.3-V signalling. AMD AthlonTM Processor System Bus Threshold AMD AthlonTM processor system bus threshold range select for AMD AthlonTM system bus I/O cells. When Low, these AMD Athlon processor system bus inputs sense input thresholds between 1.35 V and 1.9 V. When High, the inputs sense thresholds between 2.0 V and 2.2 V. AMD Athlon Processor Push-Pull Driver Enable When set, this bit indicates that the AMD Athlon processor push-pull drivers are enabled. AMD-762TM System Controller Push-Pull Driver Enable When set, this bit indicates that the AMD-762 system controller push-pull drivers are enabled. Clock Speed This bit field defines the speed of the system clock received by the AMD-762 system controller: 00 = 100 MHz 01 = 66 MHz 10 = Reserved 11 = 133 MHz 24 S2K_Thresh 23 22 K7_PP_En IG_PP_En 21-20 Clk_Speed 19-18 S2K1_Bus_Len S2K1 Bus Length This bit field indicates the relative length of the AMD Athlon processor system bus trace routing on the motherboard. 00 = Short 01.............. 10.............. 11 = Long 17-16 S2K0_Bus_Len AMD Athlon Processor System Bus Length This bit field indicates the relative length of the AMD Athlon processor system bus trace routing on the motherboard. 00 = Short 01.............. 10............... 1 = Long Chapter 2 AMD-762TM System Controller Programmer's Interface 83 Preliminary Information AMD-762TM System Controller Software/BIOS Design Guide 24462D--March 2002 Bit Definitions (Continued) Bit 15 14 13 Name Tristate_En NAND_En Bypass_PLLs Function Tristate Enable For internal test only. NAND Enable For internal test only. Config Status (Dev0:F0:0x88) Bypass PLLs This bit is set for test and debug of the AMD-762TM system controller with the internal PLLs disabled. 0 = AMD-762 system controller PLLs enabled 1 = AMD-762 system controller PLLs bypassed; clocks driven from SYSCLK and AGPCLK pins directly to internal clock trees 12 11-8 Dis_Divider CPU1_Divider Disable Divider For internal test only. CPU Divider This bit field contains the CPU clock multiplier field supplied by the processor. CPU1_Divider together with ClkSpeed and the S2K1_Bus Len field allow the AMD-762 system controller to properly program the AMD AthlonTM system bus initialization logic using the SIP protocol. The clock multiplier field is also known as the Frequency Identification (FID) bits, and the values are shown below. FID Value Multiplier FID Value Multiplier FID Value Multiplier FID Value Multiplier 0000 0001 0010 0011 11.0 11.5 12.0 12.5 0100 0101 0110 0111 5.0 5.5 6.0 6.5 1000 1001 1010 1011 7.0 7.5 8.0 8.5 1100 1101 1110 1111 9.0 9.5 10.0 10.5 7 SIP_ROM_En SIP ROM Enabled This bit indicates that the external SIP ROM is enabled and is read to create the SIP stream to the AMD Athlon processor, instead of the internally generated SIP table. 66-MHz PCI Platform 0 = This platform supports a 33-MHz (only) PCI bus. 1 = This platform supports a 66/33-MHz PCI bus. Note that this pinstrap indicates only that the motherboard is designed to support a 66-MHz PCI bus. The M66EN pin determines whether the installed card is capable of 66-MHz operation. This pinstrap is used only internally by the AMD-762 system controller to condition its PCI clock logic. 6 66MHzPCI 5 In_Clk_En INCLK Enable This bit indicates that the AMD-762 system controller delays the INCLK to the AMD Athlon processor. When reset, the motherboard is expected to provide delay in the etch to center the INCLK with the data. 84 AMD-762TM System Controller Programmer's Interface Chapter 2 Preliminary Information 24462D--March 2002 AMD-762TM System Controller Software/BIOS Design Guide Bit Definitions (Continued) Bit 4 Name Out_Clk_En Function Config Status (Dev0:F0:0x88) OUTCLK Enable This bit indicates that the AMD Athlon processor delays the OUTCLK to the AMD-762 system controller. When reset, the motherboard is expected to provide delay in the etch to center the OUTCLK with the data. CPU Divider This bit field contains the CPU clock multiplier field supplied by the processor. Together with the Clk_Speed field and the S2K0_Bus_Len field, these fields allow the AMD-762TM system controller to properly program the AMD AthlonTM processor system bus initialization logic using the SIP protocol. The clock multiplier field is also known as the Frequency Identification (FID) bits and the values are shown below. FID Value Multiplier FID Value Multiplier FID Value Multiplier FID Value Multiplier 0000 0001 0010 0011 11.0 11.5 12.0 12.5 0100 0101 0110 0111 5.0 5.5 6.0 6.5 1000 1001 1010 1011 7.0 7.5 8.0 8.5 1100 1101 1110 1111 9.0 9.5 10.0 10.5 3-0 CPU0_Divider Programming Notes Chapter 2 AMD-762TM System Controller Programmer's Interface 85 Preliminary Information AMD-762TM System Controller Software/BIOS Design Guide 24462D--March 2002 PCI Top of Memory 31 Bit Reset R/W 23 Bit Reset R/W 15 Bit Reset R/W 7 Bit Reset R/W 0 0 0 0 R 6 5 4 Reserved 0 0 0 0 0 0 0 R 3 2 1 14 13 12 Reserved 0 0 0 0 0 0 0 R 11 10 9 22 21 20 Reserved 0 0 0 1 0 0 30 29 28 27 26 PCI_Mem_Top 0 R/W 19 18 0 0 0 Dev0:F0:0x9C 25 24 0 17 16 0 8 0 0 0 Register Description This register is used to define the top of main system memory. It is used to compare the memory addresses of an external PCI master to determine if it is in the range of the AMD-762 system controller DRAM. If the address compares, then the AMD-762 system controller responds to the bus master access with DEVSEL# assertion. 86 AMD-762TM System Controller Programmer's Interface Chapter 2 Preliminary Information 24462D--March 2002 AMD-762TM System Controller Software/BIOS Design Guide Bit Definitions Bit 31-24 Name PCI_Mem_Top Function PCI Top of Memory (Dev0:F0:0x9C) PCI Memory Top This 8-bit field is compared to the incoming PCI bus master address to determine if a memory cycle falls within the AMD-762TM system controller DRAM region, as follows: 31 30 29 28 27 26 25 24 PCIMemTop Field 31 30 29 28 27 26 25 24 PCI Address BIOS should write to this field following completion of the memory sizing algorithm, after it has determined the total size of the installed memory. 23-0 Reserved Reserved Programming Notes Chapter 2 AMD-762TM System Controller Programmer's Interface 87 Preliminary Information AMD-762TM System Controller Software/BIOS Design Guide 24462D--March 2002 AGP Capability Identifier 31 Bit Reset R/W 23 Bit Reset R/W 15 Bit Reset R/W 7 Bit Reset R/W 0 0 0 0 R 6 5 4 Cap_ID 0 0 0 0 0 0 R 3 2 14 13 12 0 0 22 Major_Rev 1 0 R 11 10 0 0 21 20 0 0 0 0 R 19 18 Minor_Rev 30 29 28 Reserved 0 0 27 26 Dev0:F0:0xA0 25 24 0 0 17 16 0 0 9 8 Next_Pointer 0 0 0 0 1 0 1 0 Register Description Bit Definitions Bit 31-24 23-20 19-16 15-8 7-0 Name Reserved Major_Rev Minor_Rev Next_Pointer Cap_ID Function Reserved AGP Capability Identifier (Dev0:F0:0xA0) Major Revision Major revision of the AGP interface specification conformed to by this device. Minor Revision Minor revision of the AGP interface specification conformed to by this device. Next Pointer Pointer to the next item in the capabilities list. Must be null for the final item on the list. CapID This value indicates that this list item pertains to AGP registers. Programming Notes 88 AMD-762TM System Controller Programmer's Interface Chapter 2 Preliminary Information 24462D--March 2002 AMD-762TM System Controller Software/BIOS Design Guide AGP Status 31 Bit Reset R/W 23 Bit Reset R/W 15 Bit Reset R/W 7 Bit Reset R/W 0 Reserved 0 6 5 R4G 0 4 FW 0 R 0 0 0 14 13 Reserved 0 R 3 Reserved 0 1 2 0 0 12 0 0 0 0 R 11 10 22 21 20 Reserved 0 0 0 0 0 30 29 28 27 26 Max_ReqQ_Depth 0 R 19 18 1 1 Dev0:F0:0xA4 25 24 1 1 17 16 0 0 9 SBA 1 8 Reserved 0 1 Rates 1 0 1 Register Description Chapter 2 AMD-762TM System Controller Programmer's Interface 89 Preliminary Information AMD-762TM System Controller Software/BIOS Design Guide 24462D--March 2002 Bit Definitions Bit 31-24 Name Max_ReqQ_ Depth Reserved SBA Function AGP Status (Dev0:F0:0xA4) Maximum Command Requests This field contains the maximum number of AGP command requests that this node can manage. Reserved Sideband Addressing This field is always 1, indicating that the AMD-762TM system controller supports sideband addressing. Reserved Address Limit This bit is always 0, indicating that the AMD-762 system controller does not support addresses greater than 4 Gbytes. Fast Write Transfer This bit indicates supports of fast write transfers. 0 = Fast writes not supported 1 = Fast writes supported Reserved Rate Transfers This field indicates that the AMD-762 system controller supports 1x (bit[0]), 2x (bit[1]), and 4X (bit[2]) transfers. 23-10 9 8-6 5 Reserved R4G 4 FW 3 2-0 Reserved Rates Programming Notes Fast writes are disabled by default and are indicated in the status bit that reports this capability. Setting the FW_Enable bit in the AGP 4X Dynamic Compensation register (Dev 0:F0:0xB4, bit 7) sets the FW bit in this register to indicate support of this feature. Fast writes are enabled when both the FW_Enable bit (in the AGP 4X Dynamic Compensation register) and the Fast_Writes bit in the AGP Command register are set. AGP 4X transfers are supported and the 4X status bit is set by default in this register. This bit can be overridden by setting the 4X_Override bit in the AGP 4X Dynamic Compensation register (Dev 0:F0:0xB4, bit 6). 90 AMD-762TM System Controller Programmer's Interface Chapter 2 Preliminary Information 24462D--March 2002 AMD-762TM System Controller Software/BIOS Design Guide AGP Command 31 Bit Reset R/W 23 Bit Reset R/W 15 Bit Reset R/W 7 Bit Reset R/W 0 Reserved 0 R 6 5 R4G_En 0 0 0 0 R 4 Fast_Writes 0 R/W 3 Reserved 0 R 0 2 14 13 Reserved 0 0 0 12 0 0 0 0 R 11 10 22 21 20 Reserved 0 0 0 0 0 0 R 19 18 30 29 28 Reserved 0 0 27 26 Dev0:F0:0xA8 25 24 0 0 17 16 0 0 9 SBA_En 0 R/W 1 Data_Transfer_Mode 0 R/W 8 AGP_En 0 0 0 Register Description Chapter 2 AMD-762TM System Controller Programmer's Interface 91 Preliminary Information AMD-762TM System Controller Software/BIOS Design Guide 24462D--March 2002 Bit Definitions Bit 31-10 9 8 Name Reserved SBA_En AGP_En Function Reserved Sideband Addressing Enable When this bit is set, sideband addressing is enabled. AGP Command (Dev0:F0:0xA8) AGP Operations Enable When this bit is set, the AMD-762TM system controller accepts AGP operations. When this bit is clear, the AMD-762 system controller ignores AGP operations. Reserved 4GB Address Indicator This bit indicates that the AMD-762 system controller does not support addresses greater than 4 Gbytes. The AMD-762 system controller supports only 32-bit addresses. Fast Writes 0 = Fast writes disabled 1 = Fast writes enabled when the FW_Enable bit is also set in the AGP 4X Dynamic Compensation register (Dev 0:F0:0xB4, bit 7) Reserved Data Transfer Mode Only one bit must be set in this field to indicate the desired AGP data transfer rate. 001 = 1X AGP rate 010 = 2X AGP rate 100 = 4X AGP rate 7-6 5 Reserved R4G_En 4 Fast_Writes 3 2-0 Reserved Data_Transfer _Mode Programming Notes 92 AMD-762TM System Controller Programmer's Interface Chapter 2 Preliminary Information 24462D--March 2002 AMD-762TM System Controller Software/BIOS Design Guide AGP Virtual Address Space Size 31 Bit Reset R/W 23 Bit Reset R/W 15 Bit Reset R/W 7 Bit Reset R/W 0 0 R 6 Reserved 0 0 0 5 4 0 0 0 0 R 3 2 VA_Size 0 R/W 14 13 0 0 0 22 21 20 Reserved 0 R 12 Reserved 0 0 11 10 0 0 0 0 0 0 R 19 18 30 29 28 Reserved 0 0 27 26 Dev0:F0:0xAC 25 24 0 0 17 16 Vga_IA_En 0 0 R/W 9 8 0 0 1 0 GART_En 0 0 Register Description Chapter 2 AMD-762TM System Controller Programmer's Interface 93 Preliminary Information AMD-762TM System Controller Software/BIOS Design Guide 24462D--March 2002 Bit Definitions Bit 31-17 16 Name Reserved Vga_IA_En Function Reserved AGP Virtual Address Space Size (Dev0:F0:0xAC) ISA Address Aliasing Enable When set, this bit forces the AMD-762TM system controller to alias ISA addresses, which means that address bits [15:10] are not used in decoding. When clear, no ISA aliasing is performed and address bits [15:10] are used for decoding. Reserved Virtual Address Size This field defines the virtual address space size to be allocated to GART by the system BIOS. Prior to the execution of the system BIOS memory mapping software, system BIOS gets the amount of GART virtual address space required by the graphics controller. It sets these bits to the required value. Changing these bits automatically changes bits [30:25] in the host-PCI bridge (device 0) AGP Virtual Address Space register, offset 0x10 (see "Dev0:F0:0x10" on page 37). The size of GART virtual address space is always greater than or equal to the amount of physical system memory allocated to AGP in non-contiguous 4-Kbyte blocks. The amount of physical memory allocated to AGP is determined by operating system software. [3] [2] [1] VA_Size 0 0 0 0 1 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 32 Mbytes 64 Mbytes 128 Mbytes 256 Mbytes 512 Mbytes 1 Gbytes 2 Gbytes 15-4 3-1 Reserved VA_Size 0 GART_En GART Enable When clear, GART is not valid in this system. System BIOS does not allocate virtual address space for GART because the host-PCI bridge (device 0) AGP virtual address space, offset 0x10 (see "Dev0:F0:0x10" on page 37) is set to 0. The PCI-PCI bridge (device 1) capabilities pointer is set to point to the next item in the linked list or null if there is no other item. This bit is set by BIOS PCI enumeration routines. When set, GART is valid in this system. System BIOS allocates virtual address space for GART based upon the value in bits [3:1] above. Programming Notes 94 AMD-762TM System Controller Programmer's Interface Chapter 2 Preliminary Information 24462D--March 2002 AMD-762TM System Controller Software/BIOS Design Guide GART/AGP Mode Control 31 Bit Reset R/W 23 Bit Reset R/W 15 Bit Reset R/W 7 Bit Reset R/W 0 0 0 0 R 6 5 4 Reserved 0 0 0 0 0 0 0 R 3 2 0 22 Reserved 0 R 14 13 12 Reserved 0 0 0 11 0 0 21 20 0 0 0 0 R 19 NonGART _Snoop 0 0 R/W 10 18 30 29 28 Reserved 0 0 0 27 26 Dev0:F0:0xB0 25 24 0 17 PDC_En 0 16 Lv1_Index 0 9 8 0 1 0 0 Register Description This register provides bits to control specific features of the AMD-762 system controller AGP implementation. Chapter 2 AMD-762TM System Controller Programmer's Interface 95 Preliminary Information AMD-762TM System Controller Software/BIOS Design Guide 24462D--March 2002 Bit Definitions Bit 31-21 20 19 NonGART_Snoop Name Reserved Function Reserved Reserved GART/AGP Mode Control (Dev0:F0:0xB0) NonGART Snoop When set, this bit forces AGP accesses that are not in the GART range to cause AMD AthlonTM processor system bus probes to the processor(s). When clear, AGP addresses that fall outside of the GART range do not cause probes. Reserved 18 17 PDC_En Gart Page Directory Cache Enable This bit is used only in the two-level GART mode. It has no effect in the one-level GART mode. The GART directory is enabled only when both this bit and the AGP Features Control register (offset 02h of the memory-mapped Features and Capabilities register--see "Bar1 + 0x00" on page 150) bit 2, "GART Cache Enable", are 1s. Level 1 Index (GART Index Scheme Control) When set to 1, this bit enables the one-level GART mode. When cleared to 0, two-level GART mode is enabled. Reserved 16 Lv1_Index 15-0 Reserved Programming Notes 96 AMD-762TM System Controller Programmer's Interface Chapter 2 Preliminary Information 24462D--March 2002 AMD-762TM System Controller Software/BIOS Design Guide AGP 4X Dynamic Compensation 31 Bit Reset R/W 23 Bit Reset R/W Reserved 0 R 15 Bit Reset R/W 7 Bit Reset R/W 6 5 Comp3.3 0 0 R 4 Reserved 1 0 0 22 DisStrb 0 R/W 14 Reserved 0 0 R 3 2 PCI 0 0 0 13 12 11 0 0 21 20 X X 30 PVal X X R 19 18 X X 29 28 27 26 NVal X Dev0:F0:0xB4 25 24 X 17 16 Quantum_Cnt 0 R/W 10 Reserved 0 0 9 8 0 0 1 1 0 FW_Enable 4X_Override 0 0 R/W Always_ Do_ Compensate Compensate 0 R/W 0 Register Description Chapter 2 AMD-762TM System Controller Programmer's Interface 97 Preliminary Information AMD-762TM System Controller Software/BIOS Design Guide 24462D--March 2002 Bit Definitions Bit 31-28 Name PVal Function AGP 4X Dynamic Compensation (Dev0:F0:0xB4) P Transistor Strength Value This field reflects the P transistor strength value that was written to the non-strobed AGP I/O pads according to Table 9 on page 99. N Transistor Strength Value This field reflects the N transistor strength value that was written to the non-strobed AGP I/O pads according to Table 9 on page 99. Reserved Disable Strobe This bit allows the complimentary strobes ADSTB[1:0]# to be disabled when the AGP interface is operating in 2X mode. Setting this bit causes these pins to be driven High. Quantum Count This field is used to determine the number of 100-ms intervals that elapse before a dynamic compensation event is performed when the AlwaysCompensate bit is set. The value allows for dynamic compensation time quantums to range from 100 ms to 6.4 s. Reserved Fast Writes Override 0 = Fast writes disabled 1 = Fast writes enabled (see below) AGP fast writes are enabled by a combination of this bit and the Fast_Writes enable bit in the AGP Command register (Dev 0:F0:0xA8, bit 4). The Fast_Writes status bit in the AGP Status register (Dev 0:F0:0xA4, bit 4) is 0 by default, indicating that the AMD-762TM system controller does not support this feature. Setting this bit forces the status bit to a 1 to indicate support of fast writes. The fast writes feature is enabled only when this bit and the Fast_Writes bit in the AGP Command register (Dev 0:F0:0xA8, bit 4) are set. AGP 4X Override This bit can be set to override the value in the read-only AGP Status register (Dev 0:FD0:0xA4). By default the rates field of the AGP Status register report 4X capability, but setting this bit forces the 4X-capable bit to be 0, indicating a maximum of 2X support. Compensate for 3.3-V Signalling This bit overrides the TYPEDET# value to force an AGP auto-compensation in a 3.3-V signalling environment. This bit may be set in conjunction with the Do_Compensate bit to enable BIOS to determine which drive strength values the auto-compensation circuit selected for this motherboard. Note: This bit must be set only while the AGP interface is disabled. Setting this bit while the AGP interface is enabled results in unpredictable behavior. Reserved PCI As shown in Table 9 on page 99, this bit, along with BYP and AGP2X bits, controls the drive strength of the output buffer and whether the input buffers are single-ended or differential. 27-24 NVal 23 22 Reserved DisStrb 21-16 Quantum_Cnt 15-8 7 Reserved FW_Enable 6 4X_Override 5 Comp3.3 4-3 2 Reserved PCI 98 AMD-762TM System Controller Programmer's Interface Chapter 2 Preliminary Information 24462D--March 2002 AMD-762TM System Controller Software/BIOS Design Guide Bit Definitions (Continued) Bit 1 Name Always_ Compensate Do_Compensate Function AGP 4X Dynamic Compensation (Dev0:F0:0xB4) Always Compensate When set, dynamic compensation is performed by AGP on an ongoing basis at regular intervals. Do Compensate This bit is used to initiate a dynamic compensation command on AGP. This bit is cleared by the AMD-762TM system controller when the compensation cycle is complete. See the programming note below on recommendation for exiting bypass mode. 0 Programming Notes When transitioning from bypass enabled to disabled via the AGP Compensation Bypass register (Dev 0:F0:0xB8), the Do_Compensate bit should be set. AGP should not be subsequently enabled until the Do_Compensate bit is read back as a 0, indicating that the compensation cycle is complete. Refer to the AGP Compensation Bypass register (Dev 0:F0:0xB8) for details of bypass mode. Table 9. BYPASS 0 0 0 1 BYPASS X X X X I/O Pad Drive Strength and Input Type TYPEDET# 0 1 1 X TYPEDET# 0 0 1 1 PCI X 0 1 X PCI X X X X AGP Mode N/A N/A N/A N/A AGP Mode 4X 1X/2X 1X/2X 1X/2X Differential Single-Ended Single-Ended Single-Ended Output Drive Strength Compensated Strength AGP-1X Strength PCI Strength Bypass, User Configurable Input Type Chapter 2 AMD-762TM System Controller Programmer's Interface 99 Preliminary Information AMD-762TM System Controller Software/BIOS Design Guide 24462D--March 2002 AGP Compensation Bypass 31 Bit Reset R/W 23 Bit Reset R/W BYPXfer 1 R/W 15 Bit Reset R/W 7 Bit Reset R/W BYPStrb 1 R/W 0 6 5 Reserved 0 R 0 0 4 0 14 0 22 21 Reserved 0 R 13 12 11 10 0 0 20 0 30 29 28 27 26 BYP_PDrvXfer 0 0 0 R/W 19 PSlewXfer 0 R/W 0 18 0 BYP_NDrvXfer 0 0 Dev0:F0:0xB8 25 24 0 17 NSlewXfer 16 0 9 8 BYP_PDrvStrb 0 0 0 R/W 3 PSlewStrb 0 BYP_NDrvStrb 0 0 0 2 1 NSlewStrb 0 0 R/W 0 0 Register Description This register allows BIOS to bypass the AGP auto-compensation to directly control the AGP pad configuration. 100 AMD-762TM System Controller Programmer's Interface Chapter 2 Preliminary Information 24462D--March 2002 AMD-762TM System Controller Software/BIOS Design Guide Bit Definitions Bit 31-28 Name BYP_PDrvXfer Function AGP Compensation Bypass (Dev0:F0:0xB8) P Drive Strength Control This field is used to directly program the P transistor drive strength on all AGP pins except the data strobes. A value of 0000 is the weakest, 1111 is the strongest. This value is written to the I/O pads only when BYPXfer (bit 23) is set. N Drive Strength Control This field is used to directly program the N transistor drive strength on all AGP signals except the data strobes. A value of 0000 is the weakest, 1111 is the strongest. This value is written to the I/O pads only when BYPXfer (bit 23) is set. Bypass Enable This bit must be set to bypass the auto-compensation circuit for direct control of all AGP pads except the strobe pins. When this bit is set, the values programmed in the drive strength fields are written directly to the pads. Reserved Slew Rate Control This field is used to directly program the rise time in all AGP signals except the data strobes. This field is not affected by the BYPXfer bit. 00 = Slew rate 0 (slowest) 01 = Slew rate 1 10 = Slew rate 2 11 = Slew rate 3 (fastest) Slew Rate Control This field is used to directly program the fall time in all AGP signals except the data strobes. This field is not affected by the BYPXfer bit. 00 = Slew rate 0 (slowest) 01 = Slew rate 1 10 = Slew rate 2 11 = Slew rate 3 (fastest) 27-24 BYP_NDrvXfer 23 BYPXfer 22-20 19-18 Reserved PSlewXfer 17-16 NSlewXfer 15-12 BYP_PDrvStrb P Drive Strength Control This field is used to directly program the P transistor drive strength on the AGP data strobes (AD_STB[1:0], AD_STB[1:0]#). A value of 0000 is the weakest, 1111 is the strongest. This value is written to the I/O pads only when BYPStrb (bit 7) is set. N Drive Strength Control This field is used to directly program the N transistor drive strength on all AGP data strobes (AD_STB[1:0], AD_STB[1:0]#). A value of 0000 is the weakest, 1111 is the strongest. This value is written to the I/O pads only when BYPStrb (bit 7) is set. Bypass Enable This bit must be set to bypass the auto-compensation circuit for direct control of all AGP strobe pins (AD_STB[1:0], AD_STB[1:0]#). When this bit is set, the values programmed in the drive strength fields are written directly to the pads. Reserved 11-8 BYP_NDrvStrb 7 BYPStrb 6-4 Reserved Chapter 2 AMD-762TM System Controller Programmer's Interface 101 Preliminary Information AMD-762TM System Controller Software/BIOS Design Guide 24462D--March 2002 Bit Definitions (Continued) Bit 3-2 Name PSlewStrb Function AGP Compensation Bypass (Dev0:F0:0xB8) Slew Rate Control This field is used to directly program the rise time in all AGP data strobes (AD_STB[1:0], AD_STB[1:0]#). This field is not affected by the BYPStrb bit. 00 = Slew rate 0 (slowest) 01 = Slew rate 1 10 = Slew rate 2 11 = Slew rate 3 (fastest) 1-0 NSlewStrb Slew Rate Control This field is used to directly program the fall time in all AGP data strobes (AD_STB[1:0], AD_STB[1:0]#). This field is not affected by the BYPStrb bit. 00 = Slew rate 0 (slowest) 01 = Slew rate 1 10 = Slew rate 2 11 = Slew rate 3 (fastest) Programming Notes There are three basic modes of bypass operation, as shown in the table below. Note that compensation applies to 1.5-V signalling operation only. Auto Compensate Non-strobe Bypass Strobes All signals Bypass Modes Non-strobed signals auto-compensated while strobe signals programmed manually in bypass mode. All signals programmed manually in bypass mode. All signals auto-compensated. All signals It is possible to configure the AGP I/O pads such that the non-strobed signals are auto-compensated while the strobes are in bypass mode, but not vice-versa, as shown in the table above. Once the non-strobed signals are programmed in bypass mode, these programmed bypassed values are also written to the strobed signal I/O pads, until the strobed pads bypass values are also written. 102 AMD-762TM System Controller Programmer's Interface Chapter 2 Preliminary Information 24462D--March 2002 AMD-762TM System Controller Software/BIOS Design Guide Memory Base Address Registers (Dev0:F0:0xC0 to 0xDF) The AMD-762 system controller DDR memory controller can access up to eight banks of DRAM (four DIMMs, one bank per side). These banks are controlled by eight chip selects. These registers define how an incoming address is parsed to select only one out of the eight chip selects. BIOS software is responsible for correctly loading these registers based on data returned from the serial presence detect ROM mechanism through the SMBus implemented in the Southbridge. BIOS software must adhere to the following rules when configuring these registers: The largest banks are configured first as the lowest addressed memory, increasing addresses with decreasing size of banks available. Logically, a given chip-select N, is asserted when: (Addr[31:23] & ~CSMaskN) == (CSBaseN & ~CSMaskN) The smallest bank supported is 32 Mbytes. See Table 10 on page 104. Chapter 2 AMD-762TM System Controller Programmer's Interface 103 Preliminary Information AMD-762TM System Controller Software/BIOS Design Guide 24462D--March 2002 Table 10. DDR Memory Base Address Register Locations Memory Base Address Register 0 Memory Base Address Register 1 Memory Base Address Register 2 Memory Base Address Register 3 Memory Base Address Register 4 Memory Base Address Register 5 Memory Base Address Register 6 Memory Base Address Register 7 31 Bit Reset R/W 23 Bit Reset R/W CS_Base X R/W 15 Bit Reset R/W 7 Bit Reset R/W CS_Mask X R/W 0 0 R 6 5 Reserved 0 0 X 4 X X X X R/W 3 2 Addr_Mode 14 13 12 CS_Mask X X 0 0 0 22 21 20 X X X X R/W 19 Reserved 0 R 11 10 0 18 30 29 28 CS_Base X X 27 26 Dev0:F0:0xC0 Dev0:F0:0xC4 Dev0:F0:0xC8 Dev0:F0:0xCC Dev0:F0:0xD0 Dev0:F0:0xD4 Dev0:F0:0xD8 Dev0:F0:0xDC 25 24 X X 17 16 0 0 9 8 X X 1 0 CS_En X R/W X Register Description Note that these registers are not initialized at reset time, but must be initialized by BIOS for proper operation. This action should be done prior to attempting DRAM access. 104 AMD-762TM System Controller Programmer's Interface Chapter 2 Preliminary Information 24462D--March 2002 AMD-762TM System Controller Software/BIOS Design Guide Bit Definitions Bit 31-23 Name CS_Base Function Memory Base Address Registers 0-7 (Dev0:F0:0xC0-0xDF) Chip-Select Base This bit field defines which 8-Mbyte boundary the given bank services. Incoming addresses are compared against field, subject to the mask field in bits [15:7]. Reserved Chip-Select Mask This bit field defines what bits in the address are ignored when incoming addresses are compared to the CSBase in bits[31:23] above. If a given bit is set, the corresponding bit in the compare is ignored. Reserved Addressing Mode This bit field determines the addressing mode for this CS, based on the type of DIMM installed, according to Table 11. This addressing applies to the physical addressing on the MAA and MAB address buses. Note that modes 00 and 11 are reserved. Chip-Select Enable When set, this bank is eligible for selection by incoming addresses. When clear, this bank's chip select is not asserted and the values in [31:23] and [15:7] are ignored. 22-16 15-7 Reserved CS_Mask 6-3 2-1 Reserved Addr_Mode 0 CS_En Programming Notes Note that these registers are not initialized at reset time, but must be initialized by BIOS for proper operation. This action should be done prior to attempting DRAM access. Table 11 shows DRAM addressing modes. Table 11. Mode AMD-762TM System Controller DRAM Addressing Modes Pins Row Col 14 12 12 BK Row Col 12 12 BK 13 11 11 BK 11 11 BK 25 29 24 28 23 PC 22 27 21 26 20 10 19 9 18 8 17 7 16 6 15 5 14 4 13 3 12 11 24 27 10 23 PC 9 22 26 8 21 25 7 20 10 6 19 9 5 18 8 4 17 7 3 16 6 2 15 5 1 14 4 0 13 3 Mode 1 Addr_Mode = 01 64 Mbyte x4/8/16 128 Mbyte x4/8/16 Mode 2 Addr_Mode = 10 256 Mbyte x4/8/16 512 Mbyte x4/8/16 Chapter 2 AMD-762TM System Controller Programmer's Interface 105 Preliminary Information AMD-762TM System Controller Software/BIOS Design Guide 24462D--March 2002 2.4.4 Device 0, Function 1: DDR PDL Configuration Registers The registers defined in this section are required to implement Double Data Rate (DDR) DRAM in the AMD-762 system controller Northbridge. The function 1 registers control the 18 DDR programmable delay lines (PDL). In Table 12, the column entitled Offset consists of the register number specified in the Configuration Address register bits [7:2] concatenated with 0b00 to form a simple 1-byte offset. Table 12. Device 0, Function 1 Configuration Register Map DDR PDL Registers (Device 0, Function 1) Reserved DDR PDL Calibration Control DDR PDL Configuration 0 DDR PDL Configuration 1 DDR PDL Configuration 2 DDR PDL Configuration 3 DDR PDL Configuration 4 DDR PDL Configuration 5 DDR PDL Configuration 6 DDR PDL Configuration 7 DDR PDL Configuration 8 DDR PDL Configuration 9 DDR PDL Configuration 10 DDR PDL Configuration 11 DDR PDL Configuration 12 DDR PDL Configuration 13 DDR PDL Configuration 14 DDR PDL Configuration 15 DDR PDL Configuration 16 DDR PDL Configuration 17 DDR MDAT/DQS Pad Configuration DDR CLK/CS Pad Configuration DDR CMDB/CMDA Pad Configuration DDR MAB/MAA Pad Configuration Reserved Offset 0x00 to 0x3F 0x40 to 0x43 0x44 to 0x47 0x48 to 0x4B 0x4C to 0x4F 0x50 to 0x53 0x54 to 0x57 0x58 to 0x5B 0x5C to 0x5F 0x60 to 0x63 0x64 to 0x67 0x68 to 0x6B 0x6C to 0x6F 0x70 to 0x73 0x74 to 0x77 0x78 to 0x7B 0x7C to 0x7F 0x80 to 0x83 0x84 to 0x87 0x88 to 0x8B 0x8C to 0x8F 0x90 to 0x93 0x94 to 0x97 0x98 to 0x9B 0x9C to 0xFF Reference "Dev0:F1:0x40" on page 107 "Dev0:F1:0x44" on page 110 "Dev0:F1:0x8C" on page 113 "Dev0:F1:0x90" on page 117 "Dev0:F1:0x94" on page 120 "Dev0:F1:0x98" on page 123 106 AMD-762TM System Controller Programmer's Interface Chapter 2 Preliminary Information 24462D--March 2002 AMD-762TM System Controller Software/BIOS Design Guide DDR PDL Calibration Control 31 Bit Reset R/W 23 Bit Reset R/W 15 Bit Reset R/W 7 Bit Reset R/W SW_Recal X R/W 6 5 4 0 0 0 0 R 3 Reserved 0 R 0 2 1 14 13 12 Reserved 0 0 0 0 0 0 0 R 11 10 9 22 21 20 Reserved 0 0 0 0 0 0 0 R 19 18 30 29 28 Reserved 0 0 0 27 26 Dev0:F1:0x40 25 24 0 17 16 0 8 0 0 Use_Act_Dly Auto_Cal_En Act_Dly_Inh X W X R/W X R/W Auto_Cal_Period X R/W X Register Description This register allows BIOS control of the calibration circuit for the AMD-762TM system controller's 18 programmable delay lines. Note that this register is not initialized at reset time but must be initialized by BIOS for proper operation. This action should be done prior to attempting DRAM access. Chapter 2 AMD-762TM System Controller Programmer's Interface 107 Preliminary Information AMD-762TM System Controller Software/BIOS Design Guide 24462D--March 2002 Bit Definitions Bit 31-8 7 Name Reserved SW_Recal Function Reserved DDR PDL Calibration Control (Dev0:F1:0x40) Software Recalibration Software should write a 1 to this bit to cause recalibration of the PDLs. The hardware recomputes the Cal_Delay values for all PDLs, based on the values of their SW_Cal_Dly fields. Status of the recalibration that was initiated by writing a 1 to this bit is also indicated in this bit. After setting this bit, software should poll this bit until it becomes a 0 again. 0 = Calibration complete (default) 1 = Calibration not complete If Auto_Cal_En is set, writes to this bit are ignored. Also refer to Table 13, "PDL Calibration Modes," on page 109. Note: This bit should not be set if the system clock frequency is 66 MHz. 6 Use_Act_Dly Use Actual Delay Software should set this bit to indicate to the hardware that it has written to the Act_Dly fields and wants to update the PDLs (all 18) with the newly written Act_Delay values. Software only needs to change the Act_Delay values that are not currently at their desired values (the other Act_Dly values are simply re-applied). This method should be used only when SW_Recal and Auto_Cal_En bits are not set. If Auto_Cal_En is set, writes to this bit are ignored. Also refer to Table 13, "PDL Calibration Modes," on page 109. This bit always returns a 0 when read. Auto Calibration Mode 0 = Auto-calibration mode off (default) 1 = Auto-calibration mode on When this bit is set, all of the Cal_Dly values are recomputed periodically (according to the setting of the Auto_Cal_Period field) for all PDLs, based on the values of their SW_Cal_Dly fields. If the Act_Dly_Inh bit is not set, the Cal_Dly values are also applied to the Act_Dly. Also refer to Table 13, "PDL Calibration Modes," on page 109. Note: Once Auto_Cal_En is set to 1, clearing it makes the bit a 0, but the Auto-Calibration logic may perform one more update, depending on when the Auto_Cal_En bit is cleared. Therefore, BIOS should at least wait for the amount of time specified by the Auto_Cal_Period field after clearing the Auto_Cal_En bit before attempting to change any of the PDL parameters. Note: This bit should not be set if the system clock frequency is 66 MHz. 5 Auto_Cal_En 108 AMD-762TM System Controller Programmer's Interface Chapter 2 Preliminary Information 24462D--March 2002 AMD-762TM System Controller Software/BIOS Design Guide Bit Definitions (Continued) Bit 4 Name Act_Dly_Inh Function DDR PDL Calibration Control (Dev0:F1:0x40) Actual Delay Update Inhibit This bit configures the hardware to either update the actual PDLs (Act_Dly values) with new Cal_Delay values or not. The setting of this bit affects both auto-calibration and SWCalibration but not the Use_Act_Dly method. After an exit from power-on reset or selfrefresh, the setting of this bit determines whether the Act_Dly value is updated or not. 0 = Update all the PDLs with new Cal_Dly values in hardware after recomputation is done (default). 1 = Do not update the Actual PDL delay values after recomputation of Cal_Dly is done. Note: The internal logic tests this bit just prior to updating the Act_Dly, so the other bits in this register should be taken into consideration when writing to this bit. 3-2 1-0 Reserved Auto_Cal_Period Reserved Auto-Calibration Period This bit field defines how often auto-calibration is performed. 00 = 10000 system clocks 01 = 1000000 system clocks 10 = 10000000 system clocks 11 = Reserved BIOS should configure this field before setting the Auto_Cal_En bit, and while Auto_Cal_En is set, do not write to this field. Programming Notes Note that this register is not initialized at reset time, but must be initialized by BIOS for proper operation. This action should be done prior to attempting DRAM access. See Table 13 for PDL calibration modes. Table 13. 0 0 0 0 1 PDL Calibration Modes Use_Act_Delay 0 0 1 1 X SW_ReCal 0 1 0 1 X No action. SW_Cal_Dly values are applied. Act_Dly values are applied. Illegal combination (do not use). SW_Cal_Dly values are applied according to the Auto_Cal_Period setting. Do not set the Act_Dly or SW_Recal bits. Resultant Operation Auto_Cal_En Chapter 2 AMD-762TM System Controller Programmer's Interface 109 Preliminary Information AMD-762TM System Controller Software/BIOS Design Guide 24462D--March 2002 Table 14. DDR PDL Configuration Register Locations DDR PDL Configuration Register 0 DDR PDL Configuration Register 1 DDR PDL Configuration Register 2 DDR PDL Configuration Register 3 DDR PDL Configuration Register 4 DDR PDL Configuration Register 5 DDR PDL Configuration Register 6 DDR PDL Configuration Register 7 DDR PDL Configuration Register 8 DDR PDL Configuration Register 9 DDR PDL Configuration Register 10 DDR PDL Configuration Register 11 DDR PDL Configuration Register 12 DDR PDL Configuration Register 13 DDR PDL Configuration Register 14 DDR PDL Configuration Register 15 DDR PDL Configuration Register 16 DDR PDL Configuration Register 17 Dev0:F1:0x44 Dev0:F1:0x48 Dev0:F1:0x4C Dev0:F1:0x50 Dev0:F1:0x54 Dev0:F1:0x58 Dev0:F1:0x5C Dev0:F1:0x60 Dev0:F1:0x64 Dev0:F1:0x68 Dev0:F1:0x6C Dev0:F1:0x70 Dev0:F1:0x74 Dev0:F1:0x78 Dev0:F1:0x7C Dev0:F1:0x80 Dev0:F1:0x84 Dev0:F1:0x88 110 AMD-762TM System Controller Programmer's Interface Chapter 2 Preliminary Information 24462D--March 2002 AMD-762TM System Controller Software/BIOS Design Guide DDR PDL Configuration Registers 31 Bit Reset R/W X X X X R 23 Bit Reset R/W X X X X R/W 15 Bit Reset R/W X X X X R 7 Bit Reset R/W X X X X R/W 6 5 4 Act_Dly X X X X 3 2 1 0 14 13 12 Cal_Dly X X X X 11 10 9 8 22 21 20 19 X 18 X 17 X 16 X 30 29 28 Clk_Dly X X X X 27 26 25 24 SW_Cal_Dly Register Description These registers allow configuration of programmable delay lines 0-17. There are a total of 18 PDLs (one per DDR DQS pin in x4 mode). Note that these registers are not initialized at reset time, but must be initialized by BIOS for proper operation. This action should be done prior to attempting DRAM access, and a software initiated calibration should be forced. Chapter 2 AMD-762TM System Controller Programmer's Interface 111 Preliminary Information AMD-762TM System Controller Software/BIOS Design Guide 24462D--March 2002 Bit Definitions Bit Name 31-24 Clk_Dly DDR PDL Configuration Registers 0-17 (Dev0:F1:0x44-0x8B) Function Clock Delay This field provides the number of buffers that amount to one half-period of the system clock. Note: Upon exit from self-refresh, this bit field is updated with the number of buffers required to equal one half-period of the system clock. The value of this field depends on the operating PVT point. This field is also updated when a recalibration is done either due to Auto_Cal_En or SW_Recal. Software Calibration Delay This bit field represents the amount of delay that is required for the corresponding DQS. The typical value is 0x69 for 100-MHz DDR operation, or 0x6B for 133 MHz. This field is used to calculate the Cal_Dly value during exit from self-refresh, auto-calibration, and software-initiated recalibration. This field must be configured before setting the SW_Recal bit or the Auto_Cal_En bit, and while these bits are set, this field must not be written. BIOS writes a desired value into this field if the default DQS delays are not the desired DQS delays for any reason. The value written in this field should be 256 times the required delay as a percentage of the half-period of the system clock, and then rounded off to the nearest integer. For example, if the desired DQS delay is 43.5 percent of the system clock's half-period, the value written into this field should be 0.434 x 256 = 111 (0x6F). Note: This bit field should not be used if the system clock frequency is 66 MHz. Calibration Delay This bit field provides the last Cal_Dly value in number of buffers. Note: Upon exit from self-refresh, this bit field is updated with the number of buffers required to equal the time specified by the SW_Cal_Dly field. The value of this field depends on the operating PVT point. This field is also updated when a recalibration is done either due to Auto_Cal_En or SW_Recal. Actual Delay This bit field provides the current Act_Dly value (in number of buffers) that is in effect for the corresponding PDL. Software can read the current value of Act_Dly from this field. Software can write the desired number of buffer delays into this field. Software typically writes to this field only if auto-calibration is disabled. After writing to this field, software should also set the Use_Act_Dly bit in the PDL Calibration Control register. Upon writes to this field, the new value takes effect at the first available "safe" time after the Use_Act_Dly bit is set. Note: Upon exit from self-refresh, this bit field is updated with the number of buffers required to equal the time specified by the SW_Cal_Dly field. The value of this field depends on the operating PVT point. This field is also updated when a recalibration is done either due to Auto_Cal_En or SW_Recal (unless the Act_Dly_Inh bit in the PDL Calibration register is set). Note: Values written directly by software to this field are not PVT-independent, so this field is primarily for lab and debug use. 23-16 SW_Cal_Dly 15-8 Cal_Dly 7-0 Act_Dly Programming Notes Note that these registers are not initialized at reset time, but must be initialized by BIOS for proper operation. This action should be done prior to attempting DRAM access, and a software-initiated calibration should be forced. 112 AMD-762TM System Controller Programmer's Interface Chapter 2 Preliminary Information 24462D--March 2002 AMD-762TM System Controller Software/BIOS Design Guide DDR DQS/MDAT Pad Configuration 31 Bit Reset R/W 23 Bit Reset R/W 15 Bit Reset R/W 7 Bit Reset R/W 0 0 R 0 R 6 Reserved 0 0 X 5 4 3 PDrvDQS X R/W X Reserved 0 X 14 0 0 R 13 12 PSlewDQS X X R/W 2 1 X 11 10 0 R 22 Reserved 0 0 X 21 20 19 PDrvMDAT X R/W 9 X Reserved 0 X 30 29 28 PSlewMDAT X X R/W 18 X 27 26 Dev0:F1:0x8C 25 NSlewMDAT X X 24 17 NDrvMDAT 16 X 8 NSlewDQS X X 0 NDrvDQS X Register Description This register allows BIOS control of the DDR DQS and memory data pad drive strength and slew rate. Chapter 2 AMD-762TM System Controller Programmer's Interface 113 Preliminary Information AMD-762TM System Controller Software/BIOS Design Guide 24462D--March 2002 Bit Definitions Bit 31-30 29-27 Name Reserved PSlewMDAT Function Reserved DDR DQS/MDAT Pad Configuration (Dev0:F1:0x8C) MDAT Rising Edge Slew Rate These bits control the rising edge slew rate of the MDAT[63:0] and DM[8:0] pins. 000 = Slew rate 0 (slowest) 001 = Slew rate 1 010 = Slew rate 2 011 = Slew rate 3 100 = Slew rate 4 101 = Slew rate 5 110 = Slew rate 6 111 = Slew rate 7 (fastest) Note that the DM[8:0] pins are controlled by the PSlewDQS field when any chip select is configured for x4 DIMMs in the DRAM Mode/Status register (Dev 0:F0:0x58). MDAT Falling Edge Slew Rate These bits control the falling edge slew rate of the MDAT[63:0] and DM[8:0] pins. 000 = Slew rate 0 (slowest) 001 = Slew rate 1 010 = Slew rate 2 011 = Slew rate 3 100 = Slew rate 4 101 = Slew rate 5 110 = Slew rate 6 111 = Slew rate 7 (fastest) Note that the DM[8:0] pins are controlled by the NSlewDQS field when any chip select is configured for x4 DIMMs in the DRAM Mode/Status register (Dev 0:F0:0x58). Reserved MDAT P Transistor Drive Strength These bits control the P transistor drive strength of the MDAT[63:0] and DM[8:0] pins. 00 = Drive strength 0 (weakest) 01 = Drive strength 1 10 = Drive strength 2 11 = Drive strength 3 (strongest) Note that the DM[8:0] pins are controlled by the PDrvDQS field when any chip select is configured for x4 DIMMs in the DRAM Mode/Status register (Dev 0:F0:0x58). 26-24 NSlewMDAT 23-20 19-18 Reserved PDrvMDAT 114 AMD-762TM System Controller Programmer's Interface Chapter 2 Preliminary Information 24462D--March 2002 AMD-762TM System Controller Software/BIOS Design Guide Bit Definitions (Continued) Bit 17-16 Name NDrvMDAT Function DDR DQS/MDAT Pad Configuration (Dev0:F1:0x8C) MDAT N Transistor Drive Strength These bits control the N transistor drive strength of the MDAT[63:0] and DM[8:0] pins. 00 = Drive strength 0 (weakest) 01 = Drive strength 1 10 = Drive strength 2 11 = Drive strength 3 (strongest) Note that the DM[8:0] pins are controlled by the NDrvDQS field when any chip select is configured for x4 DIMMs in the DRAM Mode/Status register (Dev 0:F0:0x58). Reserved DQS Rising Edge Slew Rate These bits control the rising edge slew rate of the DQS[8:0] pins (and DM[8:0] pins) when any chip select is configured for x4 DIMMs in the DRAM Mode/Status register at Dev 0:F0:0x58). 000 = Slew rate 0 (slowest) 001 = Slew rate 1 010 = Slew rate 2 011 = Slew rate 3 100 = Slew rate 4 101 = Slew rate 5 110 = Slew rate 6 111 = Slew rate 7 (fastest) DQS Falling Edge Slew Rate These bits control the falling edge slew rate of the DQS[8:0] pins (and DM[8:0] pins) when any chip select is configured for x4 DIMMs in the DRAM Mode/Status register at Dev 0:F0:0x58). 000 = Slew rate 0 (slowest) 001 = Slew rate 1 010 = Slew rate 2 011 = Slew rate 3 100 = Slew rate 4 101 = Slew rate 5 110 = Slew rate 6 111 = Slew rate 7 (fastest) Reserved 15-14 13-11 Reserved PSlewDQS 10-8 NSlewDQS 7-4 Reserved Chapter 2 AMD-762TM System Controller Programmer's Interface 115 Preliminary Information AMD-762TM System Controller Software/BIOS Design Guide 24462D--March 2002 Bit Definitions (Continued) Bit 3-2 Name PDrvDQS Function DDR DQS/MDAT Pad Configuration (Dev0:F1:0x8C) DQS P Transistor Drive Strength These bits control the P transistor drive strength of the DQS[8:0] pins (and DM[8:0] pins) when any chip select is configured for x4 DIMMs in the DRAM Mode/Status register at Dev 0:F0:0x58). 00 = Drive strength 0 (weakest) 01 = Drive strength 1 10 = Drive strength 2 11 = Drive strength 3 (strongest) DQS N Transistor Drive Strength These bits control the N transistor drive strength of the DQS[8:0] pins (and DM[8:0] pins) when any chip select is configured for x4 DIMMs in the DRAM Mode/Status register at Dev 0:F0:0x58). 00 = Drive strength 0 (weakest) 01 = Drive strength 1 10 = Drive strength 2 11 = Drive strength 3 (strongest) 1-0 NDrvDQS Programming Notes 116 AMD-762TM System Controller Programmer's Interface Chapter 2 Preliminary Information 24462D--March 2002 AMD-762TM System Controller Software/BIOS Design Guide DDR CLK/CS Pad Configuration 31 Bit Reset R/W 23 Bit Reset R/W 15 Bit Reset R/W 7 Bit Reset R/W 0 0 R 0 R 6 Reserved 0 0 X 5 4 3 PDrvCS X R/W X Reserved 0 X 14 0 0 R 13 12 PSlewCS X X R/W 2 1 X 11 10 0 R 22 Reserved 0 0 X 21 20 19 PDrvCLK X R/W 9 X Reserved 0 X 30 29 28 PSlewCLK X X R/W 18 X 27 26 Dev0:F1:0x90 25 NSlewCLK X X 24 17 NDrvCLK 16 X 8 NSlewCS X X 0 NDrvCS X Register Description This register allows BIOS control of the DDR clocks and chip-selects pad drive strength and slew rate. Chapter 2 AMD-762TM System Controller Programmer's Interface 117 Preliminary Information AMD-762TM System Controller Software/BIOS Design Guide 24462D--March 2002 Bit Definitions Bit 31-30 29-27 Name Reserved PSlewCLK Function Reserved DDR CLK/CS Pad Configuration (Dev0:F1:0x90) Clocks Rising Edge Slew Rate These bits control the rising edge slew rate of the CLKOUT[5:0] and CLKOUT[5:0]# pins. 000 = Slew rate 0 (slowest) 001 = Slew rate 1 010 = Slew rate 2 011 = Slew rate 3 100 = Slew rate 4 101 = Slew rate 5 110 = Slew rate 6 111 = Slew rate 7 (fastest) Clocks Falling Edge Slew Rate These bits control the falling edge slew rate of the CLKOUT[5:0] and CLKOUT[5:0]# pins. 000 = Slew rate 0 (slowest) 001 = Slew rate 1 010 = Slew rate 2 011 = Slew rate 3 100 = Slew rate 4 101 = Slew rate 5 110 = Slew rate 6 111 = Slew rate 7 (fastest) Reserved Clocks P Transistor Drive Strength These bits control the P transistor drive strength of the CLKOUT[5:0] and CLKOUT[5:0]# pins. 00 = Drive strength 0 (weakest) 01 = Drive strength 1 10 = Drive strength 2 11 = Drive strength 3 (strongest) Clocks N Transistor Drive Strength These bits control the N transistor drive strength of the CLKOUT[5:0] and CLKOUT[5:0]# pins. 00 = Drive strength 0 (weakest) 01 = Drive strength 1 10 = Drive strength 2 11 = Drive strength 3 (strongest) Reserved 26-24 NSlewCLK 23-20 19-18 Reserved PDrvCLK 17-16 NDrvCLK 15-14 Reserved 118 AMD-762TM System Controller Programmer's Interface Chapter 2 Preliminary Information 24462D--March 2002 AMD-762TM System Controller Software/BIOS Design Guide Bit Definitions (Continued) Bit 13-11 Name PSlewCS Function DDR CLK/CS Pad Configuration (Dev0:F1:0x90) CS Rising Edge Slew Rate These bits control the rising edge slew rate of the CS[7:0]# pins. 000 = Slew rate 0 (slowest) 001 = Slew rate 1 010 = Slew rate 2 011 = Slew rate 3 100 = Slew rate 4 101 = Slew rate 5 110 = Slew rate 6 111 = Slew rate 7 (fastest) CS Falling Edge Slew Rate These bits control the falling edge slew rate of the CS[7:0]# pins. 000 = Slew rate 0 (slowest) 001 = Slew rate 1 010 = Slew rate 2 011 = Slew rate 3 100 = Slew rate 4 101 = Slew rate 5 110 = Slew rate 6 111 = Slew rate 7 (fastest) Reserved CS P Transistor Drive Strength These bits control the P transistor drive strength of the CS[7:0]# pins. 00 = Drive strength 0 (weakest) 01 = Drive strength 1 10 = Drive strength 2 11 = Drive strength 3 (strongest) CS N Transistor Drive Strength These bits control the N transistor drive strength of the CS[7:0]# pins. 00 = Drive strength 0 (weakest) 01 = Drive strength 1 10 = Drive strength 2 11 = Drive strength 3 (strongest) 10-8 NSlewCS 7-4 3-2 Reserved PDrvCS 1-0 NDrvCS Programming Notes Chapter 2 AMD-762TM System Controller Programmer's Interface 119 Preliminary Information AMD-762TM System Controller Software/BIOS Design Guide 24462D--March 2002 DDR CMDB/CMDA Pad Configuration 31 Bit Reset R/W 23 Bit Reset R/W 15 Bit Reset R/W 7 Bit Reset R/W 0 0 R 0 R 6 Reserved 0 0 X 5 4 3 PDrvCMDA X R/W X Reserved 0 X 14 0 0 R 13 12 PSlewCMDA X X R/W 2 1 X 11 10 0 R 22 Reserved 0 0 X 21 20 19 PDrvCMDB X R/W 9 X Reserved 0 X 30 29 28 PSlewCMDB X X R/W 18 X 27 26 Dev0:F1:0x94 25 NSlewCMDB X X 24 17 NDrvCMDB 16 X 8 NSlewCMDA X X 0 NDrvCMDA X Register Description This register allows BIOS control of the DDR RASA#, RASB#, CASA#, CASB#, WEA#, WEB#, CKEA#, and CKEB# pad drive strength and slew rate. 120 AMD-762TM System Controller Programmer's Interface Chapter 2 Preliminary Information 24462D--March 2002 AMD-762TM System Controller Software/BIOS Design Guide Bit Definitions Bit 31-30 29-27 Name Reserved PSlewCMDB Function Reserved DDR CMDB/CMDA Pad Configuration (Dev0:F1:0x94) Command B Rising Edge Slew Rate These bits control the rising edge slew rate of the RASB#, CASB#, WEB#, and CKEB# pins. 000 = Slew rate 0 (slowest) 001 = Slew rate 1 010 = Slew rate 2 011 = Slew rate 3 100 = Slew rate 4 101 = Slew rate 5 110 = Slew rate 6 111 = Slew rate 7 (fastest) Command B Falling Edge Slew Rate These bits control the falling edge slew rate of the RASB#, CASB#, WEB#, and CKEB# pins. 000 = Slew rate 0 (slowest) 001 = Slew rate 1 010 = Slew rate 2 011 = Slew rate 3 100 = Slew rate 4 101 = Slew rate 5 110 = Slew rate 6 111 = Slew rate 7 (fastest) Reserved Command B P Transistor Drive Strength These bits control the P transistor drive strength of the RASB#, CASB#, WEB#, and CKEB# pins. 00 = Drive strength 0 (weakest) 01 = Drive strength 1 10 = Drive strength 2 11 = Drive strength 3 (strongest) Command B N Transistor Drive Strength These bits control the N transistor drive strength of the RASB#, CASB#, WEB#, and CKEB# pins. 00 = Drive strength 0 (weakest) 01 = Drive strength 1 10 = Drive strength 2 11 = Drive strength 3 (strongest) Reserved 26-24 NSlewCMDB 23-20 19-18 Reserved PDrvCMDB 17-16 NDrvCMDB 15-14 Reserved Chapter 2 AMD-762TM System Controller Programmer's Interface 121 Preliminary Information AMD-762TM System Controller Software/BIOS Design Guide 24462D--March 2002 Bit Definitions (Continued) Bit 13-11 Name PSlewCMDA Function DDR CMDB/CMDA Pad Configuration (Dev0:F1:0x94) Command A Rising Edge Slew Rate These bits control the rising edge slew rate of the RASA#, CASA#, WEA#, and CKEA# pins. 000 = Slew rate 0 (slowest) 001 = Slew rate 1 010 = Slew rate 2 011 = Slew rate 3 100 = Slew rate 4 101 = Slew rate 5 110 = Slew rate 6 111 = Slew rate 7 (fastest) Command A Falling Edge Slew Rate These bits control the falling edge slew rate of the RASA#, CASA#, WEA#, and CKEA# pins. 000 = Slew rate 0 (slowest) 001 = Slew rate 1 010 = Slew rate 2 011 = Slew rate 3 100 = Slew rate 4 101 = Slew rate 5 110 = Slew rate 6 111 = Slew rate 7 (fastest) Reserved Command A P Transistor Drive Strength These bits control the P transistor drive strength of the RASA#, CASA#, WEA#, and CKEA# pins. 00 = Drive strength 0 (weakest) 01 = Drive strength 1 10 = Drive strength 2 11 = Drive strength 3 (strongest) Command A N Transistor Drive Strength These bits control the N transistor drive strength of the RASA#, CASA#, WEA#, and CKEA# pins. 00 = Drive strength 0 (weakest) 01 = Drive strength 1 10 = Drive strength 2 11 = Drive strength 3 (strongest) 10-8 NSlewCMDA 7-4 3-2 Reserved PDrvCMDA 1-0 NDrvCMDA Programming Notes 122 AMD-762TM System Controller Programmer's Interface Chapter 2 Preliminary Information 24462D--March 2002 AMD-762TM System Controller Software/BIOS Design Guide DDR MAB/MAA Pad Configuration 31 Bit Reset R/W 23 Bit Reset R/W 15 Bit Reset R/W 7 Bit Reset R/W 0 0 R 0 R 6 Reserved 0 0 X 5 4 3 PDrvMAA X R/W X Reserved 0 X 14 0 0 R 13 12 PSlewMAA X X R/W 2 1 X 11 10 0 R 22 Reserved 0 0 X 21 20 19 PDrvMAB X R/W 9 X Reserved 0 X 30 29 28 PSlewMAB X X R/W 18 X 27 26 Dev0:F1:0x98 25 NSlewMAB X X 24 17 NDrvMAB 16 X 8 NSlewMAA X X 0 NDrvMAA X Register Description This register allows BIOS control of the DDR MAA and MAB address bus pad drive strength and slew rate. Chapter 2 AMD-762TM System Controller Programmer's Interface 123 Preliminary Information AMD-762TM System Controller Software/BIOS Design Guide 24462D--March 2002 Bit Definitions Bit 31-30 29-27 Name Reserved PSlewMAB Function Reserved DDR MAB/MAA Pad Configuration (Dev0:F1:0x98) MAB Rising Edge Slew Rate These bits control the rising edge slew rate of the MAB[14:0] pins. 000 = Slew rate 0 (slowest) 001 = Slew rate 1 010 = Slew rate 2 011 = Slew rate 3 100 = Slew rate 4 101 = Slew rate 5 110 = Slew rate 6 111 = Slew rate 7 (fastest) MAB Falling Edge Slew Rate These bits control the falling edge slew rate of the MAB[14:0] pins. 000 = Slew rate 0 (slowest) 001 = Slew rate 1 010 = Slew rate 2 011 = Slew rate 3 100 = Slew rate 4 101 = Slew rate 5 110 = Slew rate 6 111 = Slew rate 7 (fastest) Reserved MAB P Transistor Drive Strength These bits control the P transistor drive strength of the MAB[14:0] pins. 00 = Drive strength 0 (weakest) 01 = Drive strength 1 10 = Drive strength 2 11 = Drive strength 3 (strongest) MAB N Transistor Drive Strength These bits control the N transistor drive strength of the MAB[14:0] pins. 00 = Drive strength 0 (weakest) 01 = Drive strength 1 10 = Drive strength 2 11 = Drive strength 3 (strongest) Reserved 26-24 NSlewMAB 23-20 19-18 Reserved PDrvMAB 17-16 NDrvMAB 15-14 Reserved 124 AMD-762TM System Controller Programmer's Interface Chapter 2 Preliminary Information 24462D--March 2002 AMD-762TM System Controller Software/BIOS Design Guide Bit Definitions (Continued) Bit 13-11 Name PSlewMAA Function DDR MAB/MAA Pad Configuration (Dev0:F1:0x98) MAA Rising Edge Slew Rate These bits control the rising edge slew rate of the MAA[14:0] pins. 000 = Slew rate 0 (slowest) 001 = Slew rate 1 010 = Slew rate 2 011 = Slew rate 3 100 = Slew rate 4 101 = Slew rate 5 110 = Slew rate 6 111 = Slew rate 7 (fastest) MAA Falling Edge Slew Rate These bits control the falling edge slew rate of the MAA[14:0] pins. 000 = Slew rate 0 (slowest) 001 = Slew rate 1 010 = Slew rate 2 011 = Slew rate 3 100 = Slew rate 4 101 = Slew rate 5 110 = Slew rate 6 111 = Slew rate 7 (fastest) Reserved MAA P Transistor Drive Strength These bits control the P transistor drive strength of the MAA[14:0] pins. 00 = Drive strength 0 (weakest) 01 = Drive strength 1 10 = Drive strength 2 11 = Drive strength 3 (strongest) MAA N Transistor Drive Strength These bits control the N transistor drive strength of the MAA[14:0] pins. 00 = Drive strength 0 (weakest) 01 = Drive strength 1 10 = Drive strength 2 11 = Drive strength 3 (strongest) 10-8 NSlewMAA 7-4 3-2 Reserved PDrvMAA 1-0 NDrvMAA Programming Notes Chapter 2 AMD-762TM System Controller Programmer's Interface 125 Preliminary Information AMD-762TM System Controller Software/BIOS Design Guide 24462D--March 2002 2.4.5 Device 1: PCI-to-PCI Bridge Configuration Registers The registers defined in this section are required to implement the PCI-to-PCI bridge function (device 1) in the AMD-762 system controller Northbridge. In Table 15, the column entitled Offset consists of the register number specified in the Configuration Address register bits [7:2] concatenated with 0b00 to form a simple 1-byte offset. Table 15. Device 1 Configuration Register Map PCI-to-PCI Bridge (Device 1) Device ID Status Class Code0x0600 Vendor ID Command Revision ID Primary Latency Timer Secondary Bus Num I/O Limit Reserved Offset 0x00 0x04 0x08 0x0C 0x10 to 0x17 Primary Bus Num I/O Base 0x18 0x1C 0x20 0x24 0x28 to 0x2F I/O Base Upper 16 Bits Reserved Interrupt Pin Interrupt Line 0x30 0x34 to 0x3B 0x3C 0x40 0x44 to 0xFF "Dev1:0x3C" on page 144 "Dev1:0x40" on page 146 "Dev1:0x30" on page 143 "Dev1:0x18" on page 134 "Dev1:0x1C" on page 136 "Dev1:0x20" on page 139 "Dev1:0x24" on page 141 Reference "Dev1:0x00" on page 127 "Dev1:0x04" on page 129 "Dev1:0x08" on page 132 "Dev1:0x0C" on page 133 Reserved Header Type Reserved SecLatency Time Subordinate Bus Num Secondary Status Memory Limit Prefetchable Memory Limit Memory Base Prefetchable Memory Base Reserved I/O Limit Upper 16 Bits Reserved Bridge Control Miscellaneous Device 1 Control Reserved 126 AMD-762TM System Controller Programmer's Interface Chapter 2 Preliminary Information 24462D--March 2002 AMD-762TM System Controller Software/BIOS Design Guide AGP/PCI ID 31 Bit Reset R/W 23 Bit Reset R/W 15 Bit Reset R/W 7 Bit Reset R/W 0 0 1 0 R 6 5 4 Vend_ID 0 0 1 0 0 0 1 R 3 2 1 14 13 12 Vend_ID 0 0 0 0 0 0 0 R 11 10 9 22 21 20 Dev_ID 1 1 0 0 1 1 1 R 19 18 17 30 29 28 Dev_ID 0 0 0 27 26 25 Dev1:0x00 24 0 16 1 8 0 0 0 Register Description Chapter 2 AMD-762TM System Controller Programmer's Interface 127 Preliminary Information AMD-762TM System Controller Software/BIOS Design Guide 24462D--March 2002 Bit Definitions Bit 31-16 Name Dev_ID Function AGP/PCI ID (Dev1:0x00) Device Identifier This 16-bit register is assigned by the device manufacturer and identifies the type of device. The current Northbridge device ID assignments are: AMD-761TM system controller -- AMD AthlonTM processor, 1P DDR 133 MHz 0x700E host to PCI bridge 0x700F PCI-to-PCI bridge (4X AGP) AMD-762TM system controller -- AMD Athlon processor, 2P DDR 133 MHz 0x700C host to PCI bridge 0x700D PCI-to-PCI bridge (4X AGP) AMD-751TM system controller -- AMD Athlon processor, 1P SDRAM-100 0x7006 host to PCI bridge 0x7007 PCI-to-PCI bridge (1X/2X AGP) 15-0 Vend_ID Vendor Identifier This 16-bit register identifies the manufacturer of the device. Programming Notes 128 AMD-762TM System Controller Programmer's Interface Chapter 2 Preliminary Information 24462D--March 2002 AMD-762TM System Controller Software/BIOS Design Guide AGP/PCI Command and Status 31 Bit Reset R/W PERR_Rcv 0 R 23 Bit Reset R/W 15 Bit Reset R/W 7 Bit Reset R/W STEP 0 6 PERR 0 5 VGA 0 R 0 0 0 14 13 Reserved 0 R 4 MWINV 0 3 SCYC 0 2 MSTR 0 1 MEM 0 R/W 0 0 12 Fast_B2B 0 30 SERR_Rcv 0 R/W1C 22 UDF 0 21 66M 1 20 Cap_Lst 0 R 11 10 9 FBACK 0 0 0 19 29 Mas_ABRT 0 28 Trgt_ABRT 0 27 Trgt_ABRTS _Signaled 0 R 18 Reserved 0 17 26 25 Dev1:0x04 24 Data_PERR 0 DEVSEL_Timing 0 1 16 0 8 SERR 0 R/W 0 I/O 0 Register Description The AGP/PCI Command and Status register provides coarse control over the PCI-PCI bridge function within the AMD-762 system controller. This register controls the ability to generate and respond to PCI cycles on both the AGP bus and the PCI bus. Chapter 2 AMD-762TM System Controller Programmer's Interface 129 Preliminary Information AMD-762TM System Controller Software/BIOS Design Guide 24462D--March 2002 Bit Definitions Bit 31 Name PERR_Rcv Function AGP/PCI Command and Status (Dev1:0x04) Detected Parity Error This bit is always Low because the AMD-762TM system controller does not support parity checking. Signaled System Error This bit is set whenever the AMD-762 system controller received AGP SERR# and subsequently asserted PCI SERR#. This bit is cleared by writing a 1. Refer to Table 7 on page 34 for details about SERR# assertion and status. Received Master Abort This bit is always 0. Receive Target Abort This bit is always 0. Signaled Target Abort This bit is always 0. DEVSEL# Timing This field is always 0b01, indicating that the AMD-762 system controller supports medium DEVSEL# timing. Data PERR# This bit is always 0 because the AMD-762 system controller does not report data parity errors. Fast Back-to-Back Capable This bit is always 0, indicating that the AMD-762 system controller as a target is not capable of accepting fast back-to-back transactions when the transactions are not to the same agent. User-Definable Features This bit is always 0, indicating that UDF is not supported on the AMD-762 system controller. 66-MHz Capable This bit is always 1, indicating that the AMD-762 system controller supports 66 MHz on device 1. Capabilities List This bit is always 0, indicating that the configuration space of this device does not support a capabilities list. Reserved Fast Back-to-Back to Different Devices Enable This bit is always 0, because the AMD-762 system controller does not allow generation of fast back-to-back transactions to different agents. 30 SERR_Rcv 29 28 27 26:25 Mas_ABRT Trgt_ABRT Trgt_ABRTS _Signaled DEVSEL_Timing 24 Data_PERR 23 Fast_B2B 22 UDF 21 66M 20 Cap_Lst 19-10 9 Reserved FBACK 130 AMD-762TM System Controller Programmer's Interface Chapter 2 Preliminary Information 24462D--March 2002 AMD-762TM System Controller Software/BIOS Design Guide Bit Definitions (Continued) Bit 8 Name SERR Function AGP/PCI Command and Status (Dev1:0x04) System Error Enable When set, this bit enables the SERR# output. When clear, this bit disables the SERR# output. The AGP A_SERR# is an input to the AMD-762TM system controller. The AMD-762 system controller receives AGP A_SERR#, ORs it with the normal PCI SERR#, and asserts it to the AMD-768TM or AMD-766TM peripheral bus controller for possible error interrupt generation. Refer to Table 7 on page 34 for details about SERR# assertion and status. Address Stepping This bit is always 0 because the AMD-762 system controller does not perform address stepping. Parity Error Response This bit is always 0 because the AMD-762 system controller does not report data parity errors. VGA Palette Snoop Enable This bit is always 0, indicating that the AMD-762 system controller does not snoop the VGA palette address range. Memory Write and Invalidate Enable This bit is always 0 because the AMD-762 system controller does not generate memory write and invalidate commands. Special Cycle This bit is always 0 because the AMD-762 system controller ignores PCI special cycles. Bus Master Enable When this bit is set, the AMD-762 system controller accepts DMA accesses from the AGP interface. Memory Access Enable When set, the AMD-762 system controller forwards AMD AthlonTM processor system bus accesses that reference AGP memory space onto the AGP bus (see "Dev1:0x20" on page 139). I/O Access Enable When set, the AMD-762 system controller forwards CPU accesses that reference AGP I/O space onto the AGP bus (see "Dev1:0x1C" on page 136). 7 STEP 6 PERR 5 VGA 4 MWINV 3 2 SCYC MSTR 1 MEM 0 I/O Programming Notes Chapter 2 AMD-762TM System Controller Programmer's Interface 131 Preliminary Information AMD-762TM System Controller Software/BIOS Design Guide 24462D--March 2002 AGP/PCI Revision ID and Class Code 31 Bit Reset R/W 23 Bit Reset R/W 15 Bit Reset R/W 7 Bit Reset R/W 0 0 0 0 R 6 5 4 Rev_ID 0 0 0 0 0 0 0 R 3 2 1 14 13 12 Prog_I/F 0 0 0 0 0 0 22 21 20 0 0 0 0 R 19 18 17 30 29 28 Class_Code 0 1 1 27 26 25 Dev1:0x08 24 0 16 Sub-Class_Code 0 R 11 10 9 8 0 1 0 0 0 0 0 Register Description Bit Definitions Bit Name 31-24 Class_Code 23-16 15-8 7-0 Sub-Class_Code Prog_I/F Rev_ID AGP/PCI Revision ID and Class Code (Dev1:0x08) Function Class Code This field is always 06h, indicating that it is a bridge device. Sub-Class Code This field is always 04h for sub-class code and 00h for Prog. I/F, indicating it is a PCI/PCI bridge. Program Interface This field is always 00h, indicating that it is a PCI-to-PCI bridge. Revision ID This field contains an 8-bit value identifying the revision number of the device. Programming Notes 132 AMD-762TM System Controller Programmer's Interface Chapter 2 Preliminary Information 24462D--March 2002 AMD-762TM System Controller Software/BIOS Design Guide AGP/PCI Header Type 31 Bit Reset R/W 23 Bit Reset R/W 15 Bit Reset R/W 7 Bit Reset R/W 0 0 0 0 R 6 5 4 Reserved 0 0 0 0 0 0 14 13 12 0 0 0 0 R 11 10 9 22 21 20 0 0 0 0 R 19 18 17 30 29 28 Reserved 0 0 0 27 26 25 Dev1:0x0C 24 0 16 Header_Type 0 0 0 1 8 Pri_Lat_Timer 0 R/W 3 2 1 0 0 0 0 0 0 Register Description Bit Definitions Bit 31-24 23-16 Name Reserved Header_Type Function Reserved AGP/PCI Header Type (Dev1:0x0C) Header Type Bit 23 is always 0, indicating that the AMD-762TM system controller is a single function device. Bits 22:16 are 0x01, indicating that type 01 configuration space header format is supported (PCI-to-PCI bridge). Primary Latency Timer This latency timer is not used in the AMD-762 system controller because the primary bus of the PCI-to-PCI bridge is internal. This register is read/write to maintain compliance with the PCI specifications. Reserved 15-8 Pri_Lat_Timer 7-0 Reserved Programming Notes Chapter 2 AMD-762TM System Controller Programmer's Interface 133 Preliminary Information AMD-762TM System Controller Software/BIOS Design Guide 24462D--March 2002 AGP/PCI Sub Bus Number/Secondary Latency Timer 31 Bit Reset R/W 23 Bit Reset R/W 15 Bit Reset R/W 7 Bit Reset R/W 0 0 0 6 5 4 0 0 0 14 13 12 0 0 0 22 21 20 0 0 0 30 29 28 27 26 25 Secon_Lat_Timer 0 R/W 19 18 17 0 0 0 Dev1:0x18 24 0 16 Sub-Bus_Num 0 R/W 11 10 9 8 0 0 0 0 Secon_Bus_Num 0 R/W 3 2 1 0 0 0 0 0 Pri_Bus_Num 0 R/W 0 0 0 0 Register Description 134 AMD-762TM System Controller Programmer's Interface Chapter 2 Preliminary Information 24462D--March 2002 AMD-762TM System Controller Software/BIOS Design Guide Bit Definitions Bit 31-24 Name Secon_Lat_Timer Function AGP/PCI Sub Bus Number/Secondary Latency Timer (Dev1:0x18) Secondary Latency Timer Adheres to the definition of the latency timer in the PCI Local Bus Specification, Revision 2.2, but only applies to the secondary interface of a PCI-to-PCI bridge. Sub-Bus Number This bit field records the number of the highest numbered PCI bus that is behind (or subordinate to) a bridge. The bridge uses this number in conjunction with the Secondary Bus Number register to determine when to respond to type 1 configuration transactions on the primary interface and to pass them on to the secondary interface. Secondary Bus Number This bit field records the number of the PCI bus that the secondary interface of the bridge is connected to. The bridge uses this number to determine when to respond to type 1 configuration transactions on the primary interface and to convert them to type 0 transactions on the secondary interface. Primary Bus Number This bit field records the number of the PCI bus that the primary interface of the bridge is connected to. The bridge uses this number to decode type 1 configuration transactions on the secondary interface that should be converted to special cycle transactions on the primary interface. 23-16 Sub-Bus_Num 15-8 Secon_Bus_Num 7-0 Pri_Bus_Num Programming Notes The AGP bus is logically a sub-bus of the PCI bus. The PCI bus normally enumerates as bus 0 and the AGP bus enumerates as bus 1. Chapter 2 AMD-762TM System Controller Programmer's Interface 135 Preliminary Information AMD-762TM System Controller Software/BIOS Design Guide 24462D--March 2002 AGP/PCI Status, I/O Base and Limit 31 Bit Reset R/W PERR_Rcv 0 R 23 Bit Reset R/W 15 Bit Reset R/W 7 Bit Reset R/W 0 6 0 14 13 12 Fast_B2B 0 22 UDF 0 30 SERR_Rcv 0 29 Mas_ABRT 0 R/W1C 21 66M 1 20 Cap_Lst 0 R 11 10 IO_Lim_R 0 0 0 R 5 4 3 2 IO_Base_R 0 0 0 R 0 1 0 9 0 0 19 18 Reserved 0 28 Trgt_ABRT 0 27 Trgt_ABRTS _Signaled 0 26 25 Dev1:0x1C 24 Data_PERR 0 DEVSEL_Timing 0 R 17 1 16 0 8 IO_Lim[15:12] 0 R/W 0 1 0 IO_Base[15:12] 0 R/W 0 1 Register Description The Secondary Status register reflects the conditions of the secondary PCI-to-PCI bridge interface (the AGP bus). The I/O Base register defines the bottom (inclusive) of an address range that is used by the bridge to determine when to forward I/O transactions from one interface to the other. The I/O Limit register defines the top (inclusive) of an address range that is used by the bridge to determine when to forward I/O transactions from one interface to the other. 136 AMD-762TM System Controller Programmer's Interface Chapter 2 Preliminary Information 24462D--March 2002 AMD-762TM System Controller Software/BIOS Design Guide Bit Definitions Bit Name 31 PERR_Rcv 30 SERR_Rcv 29 Mas_ABRT 28 27 Trgt_ABRT Trgt_ABRTS _Signaled DEVSEL_Timing 26-25 24 23 Data_PERR Fast_B2B 22 21 UDF 66M 20 Cap_Lst 19-16 15-12 Reserved IO_Lim[15:12] 11-8 IO_Lim_R AGP/PCI Status, I/O Base and Limit (Dev1:0x1C) Function Detected Parity Error This bit is always Low because the AMD-762TM system controller does not support parity checking. Signaled System Error This bit is set whenever the AMD-762 system controller received AGP SERR#. This bit is cleared by writing a 1. Refer to Table 7 on page 34 for details about SERR# assertion and status. Received Master Abort This bit is set by the AMD-762 system controller whenever a bus master transaction (except for a special cycle) is terminated due to a master abort. This bit is cleared by writing a 1. Receive Target Abort This bit is set by the AMD-762 system controller whenever a bus master transaction (except for a special cycle) is terminated due to a target abort. This bit is cleared by writing a 1. Signaled Target Abort This bit is always 0 because the AMD-762 system controller does not terminate transactions with target aborts. DEVSEL# Timing This field is always 0x1, indicating that the AMD-762 system controller supports medium DEVSEL# timing. Data PERR# This bit is always 0 because the AMD-762 system controller does not report data parity errors. Fast Back-to-Back Capable This bit is always 0, indicating that the AMD-762 system controller as a target is not capable of accepting fast back-to-back transactions when the transactions are not to the same agent. User-Definable Features This bit is always 0, indicating that UDF is not supported on the AMD-762 system controller. 66-MHz Capable This bit is always 1, indicating that the AMD-762 system controller supports 66 MHz on device 1. Capabilities List This bit is always 0, indicating that the configuration space of this device does not support a capabilities list. Reserved I/O Limit (Write) This bit field indicates the upper writable 4 bits that define the top address of an address range that is used by the bridge to determine when to forward I/O transactions from one interface to the other. I/O Limit (Read) The lower read-only 4 bits define the top address of an address range that is used by the bridge to determine when to forward I/O transactions from one interface to the other. 0x1 indicates that 32-bit I/O address decoding is available. Chapter 2 AMD-762TM System Controller Programmer's Interface 137 Preliminary Information AMD-762TM System Controller Software/BIOS Design Guide 24462D--March 2002 Bit Definitions (Continued) AGP/PCI Status, I/O Base and Limit (Dev1:0x1C) Bit Name Function 7-4 IO_Base[15:12] I/O Base (Write) The upper writable 4 bits define the bottom address of an address range that is used by the bridge to determine when to forward I/O transactions from one interface to the other. 3-0 IO_Base_R I/O Base (Read) The lower read-only 4 bits define the bottom address of an address range that is used by the bridge to determine when to forward I/O transactions from one interface to the other. 0x1 indicates that 32-bit I/O address decoding is available. Programming Notes 138 AMD-762TM System Controller Programmer's Interface Chapter 2 Preliminary Information 24462D--March 2002 AMD-762TM System Controller Software/BIOS Design Guide AGP/PCI Memory Limit and Base 31 Bit Reset R/W 23 Bit Reset R/W 15 Bit Reset R/W 7 Bit Reset R/W 0 6 MBase[31:20] 0 R/W 0 0 0 0 R 5 4 0 0 0 14 0 0 R/W 13 12 11 10 22 MLim[31:20] 0 0 0 0 R 9 21 20 0 0 0 0 R/W 19 18 Reserved 0 17 30 29 28 27 26 25 MLim[31:20] 0 0 0 Dev1:0x20 24 0 16 0 8 MBase[31:20] 0 R/W 3 2 Reserved 0 0 1 0 0 0 0 0 Register Description Chapter 2 AMD-762TM System Controller Programmer's Interface 139 Preliminary Information AMD-762TM System Controller Software/BIOS Design Guide 24462D--March 2002 Bit Definitions Bit 31-20 Name MLim[31:20] Function AGP/PCI Memory Limit and Base (Dev1:0x20) Memory Limit Address Memory limit address defines the top address of the non-prefetchable address range used by the AGP target (graphics controller) where control registers and FIFO-like communication interfaces are mapped. The lower 20 bits of address are assumed to be 0xFFFFF. The memory address range adheres to 1-Mbyte alignment and granularity. Reserved Memory Base Address Memory Base Address defines the base address of the non-prefetchable address range used by the AGP target (graphics controller) where control registers and FIFO-like communication interfaces are mapped. Bits [15:4] correspond to address bits [31:20]. The lower 20 bits of the address are assumed to be 0. The memory address range adheres to 1-Mbyte alignment and granularity. Reserved 19-16 15-4 Reserved MBase[31:20] 3-0 Reserved Programming Notes 140 AMD-762TM System Controller Programmer's Interface Chapter 2 Preliminary Information 24462D--March 2002 AMD-762TM System Controller Software/BIOS Design Guide AGP/PCI Prefetchable Memory Limit and Base 31 Bit Reset R/W 23 Bit Reset R/W 15 Bit Reset R/W 7 Bit Reset R/W 0 6 5 4 0 0 0 14 0 22 21 20 0 0 0 30 29 28 27 26 25 Prefet_Mem_Lim 0 R/W 19 18 Reserved 0 0 0 R 13 12 11 10 9 0 17 0 0 0 Dev1:0x24 24 0 16 Prefet_Mem_Lim 0 R/W 0 0 8 Prefet_Mem_Base 0 R/W 3 2 Reserved 0 0 0 R 0 0 1 0 0 0 0 0 Prefet_Mem_Base 0 R/W 0 Register Description Chapter 2 AMD-762TM System Controller Programmer's Interface 141 Preliminary Information AMD-762TM System Controller Software/BIOS Design Guide 24462D--March 2002 Bit Definitions Bit Definitions Bit 31-20 Name Prefet_Mem_Lim Function Prefetchable Memory Limit Address Prefetchable memory limit address defines the top address of the prefetchable address range used by the AGP target (graphics controller) where control registers and FIFO-like communication interfaces are mapped. The lower 20 bits of address are assumed to be 0xFFFFF. The memory address range adheres to 1-Mbyte alignment and granularity. Reserved Prefetchable Memory Base Address Prefetchable memory base address defines the base address of the prefetchable address range used by the AGP target (graphics controller) where control registers and FIFO-like communication interfaces are mapped. Bits [15:4] correspond to address bits [31:20]. The lower 20 bits of the address are assumed to be 0. The memory address range adheres to 1-Mbyte alignment and granularity. Reserved AGP/PCI Prefetchable Memory Limit and Base (Dev1:0x24) 19-16 15-4 Reserved Prefet_Mem_Base 3-0 Reserved Programming Notes 142 AMD-762TM System Controller Programmer's Interface Chapter 2 Preliminary Information 24462D--March 2002 AMD-762TM System Controller Software/BIOS Design Guide AGP/PCI I/O Limit and Base Upper 16 Bits 31 Bit Reset R/W 23 Bit Reset R/W 15 Bit Reset R/W 7 Bit Reset R/W 0 0 0 6 5 4 0 0 0 0 R 3 2 1 14 13 12 Reserved 0 0 0 0 0 0 22 21 20 0 0 0 0 R 19 18 17 30 29 28 Reserved 0 0 0 27 26 25 Dev1:0x30 24 0 16 I/O_Lim[23:16] 0 R/W 11 10 9 8 0 0 0 0 0 0 I/O_Base[23:16] 0 R/W 0 0 0 0 Register Description This set of registers define the valid range of 32-bit I/O addresses that are allowed to be forwarded from the host to the AGP/PCI. Note that if this register is 0, 32-bit addressing mode is effectively disabled. Bit Definitions Bit 31-24 23-16 Name Reserved I/O_Lim[23:16] Function Reserved I/O Limit This field defines the upper limit (inclusive) of 24-bit I/O addresses that are passed to the AGP/PCI bus. Reserved I/O Base This field defines the base (inclusive) of 24-bit I/O addresses that are passed to the AGP/PCI bus. AGP/PCI I/O Limit and Base Upper 16 Bits (Dev1:0x30) 15-8 7-0 Reserved I/O_Base[23:16] Programming Notes Chapter 2 AMD-762TM System Controller Programmer's Interface 143 Preliminary Information AMD-762TM System Controller Software/BIOS Design Guide 24462D--March 2002 AGP/PCI Interrupt and Bridge Control 31 Bit Reset R/W 23 Bit Reset R/W 15 Bit Reset R/W 7 Bit Reset R/W 0 0 0 0 R/W 6 5 0 0 0 0 14 Bridge_Fast _B2B_En 0 22 Secon_Bus _Reset 0 R 13 12 Int_Pin 0 0 0 11 21 Mas_Abort _Mode 0 20 Reserved 0 0 0 0 0 R 19 VGA_En 0 18 ISA_En 0 R/W 10 9 17 SERR_En 0 30 29 28 Reserved 0 0 0 27 26 25 Dev1:0x3C 24 0 16 Par_Resp_En 0 R 8 0 R/W (See Note) 4 Int_Line 0 0 0 0 3 2 1 0 Register Description Bit Definitions Bit 31-24 23 Name Reserved Bridge_Fast_ B2B_En Function Reserved AGP/PCI Interrupt and Bridge Control (Dev1:0x3C) Fast Back-to-Back Capable This bit is always 0, indicating that the AMD-762TM system controller as a master is not capable of generating fast back-to-back transactions to different agents on the secondary bus. Secondary Bus Reset This bit is always 0. Reset for the secondary interface is done with the PCIRST# output of the AMD-768TM or AMD-766TM peripheral bus controller. Master Abort Mode This bit is always 0. The response to a master abort is determined by the RD_Data_Err_Dis bit, Dev0:F0:0x84 bit 12. 22 Secon_Bus_Reset 21 Mas_Abort_Mode 144 AMD-762TM System Controller Programmer's Interface Chapter 2 Preliminary Information 24462D--March 2002 AMD-762TM System Controller Software/BIOS Design Guide Bit Definitions (Continued) Bit 20 19 Name Reserved VGA_En Function Reserved AGP/PCI Interrupt and Bridge Control (Dev1:0x3C) VGA Enable Affects the response by the bridge to compatible VGA addresses. When it is set, the bridge decodes and forwards the following accesses on the primary interface to the secondary interface. Memory accesses in the range: 0xA0000 to 0xBFFFF I/O address where AD[9:0] are in the ranges: 0x3B0 to 0x3BB and 0x3C0 to 0x3DF (inclusive of ISA address aliases -- AD[15:10] are not decoded) 18 ISA_En ISA Enable Modifies the response by the bridge to ISA I/O addresses. This modification applies only to I/O addresses that are enabled by the I/O Base and I/O Limit registers and are in the first 64 Kbytes of PCI I/O address space (0000 0000h to 0000 FFFFh). When set, the bridge blocks any forwarding from primary to secondary of I/O transactions addressing the last 768 bytes in each 1-Kbyte block. In the opposite direction (secondary to primary), I/O transactions are forwarded if they address the last 768 bytes in each 1-Kbyte block. 0 = Forward all I/O addresses in the address range defined by the I/O Base and I/O Limit registers. 1 = Block forwarding of ISA I/O addresses in the address range defined by the I/O Base & I/O Limit registers that are in the first 64 Kbytes of PCI I/O address space (top 768 bytes of each 1-Kbyte block). 17 SERR_En SERR Enable Forwards the secondary interface SERR# assertions to the primary interface. This bit must be set, along with the SERR enable bit (Dev 1:F0:0x04) to allow an AGP SERR# to be propagated to the AMD-762TM system controller PCI SERR# pin. Refer to Table 7 on page 34 for details about SERR# assertion and status. Parity Response Enable This bit is always 0. The AMD-762 system controller does not support parity. Interrupt Pin Indicates which interrupt pin the PCI-to-PCI bridge uses. Note: This field is R/W depending on the value of the IntPinCntl bit (Bit 0 of Dev 1:0x40). Refer to "Dev1:0x40" on page 146 for details. The ability to write this field is supported to allow BIOS to program to the required value. The AMD-762 system controller hardware does not use this field internally in any way. Interrupt Line Communicates interrupt line routing information. This field is a simple R/W field to allow BIOS software to program to the required value. 16 15-8 Par_Resp_En Int_Pin 7-0 Int_Line Programming Notes Chapter 2 AMD-762TM System Controller Programmer's Interface 145 Preliminary Information AMD-762TM System Controller Software/BIOS Design Guide 24462D--March 2002 Miscellaneous Device 1 Control 31 Bit Reset R/W 23 Bit Reset R/W 15 Bit Reset R/W 7 Bit Reset R/W 0 0 0 6 5 4 Reserved 0 R 0 0 0 0 0 0 0 R 3 2 1 14 13 12 Reserved 0 0 0 0 0 0 0 R 11 10 9 22 21 20 Reserved 0 0 0 0 0 0 0 R 19 18 17 30 29 28 Reserved 0 0 0 27 26 25 Dev1:0x40 24 0 16 0 8 0 0 Int_Pin_Cntl 0 R/W Register Description Bit Definitions Bit 31-1 0 Name Reserved Int_Pin_Cntl Function Reserved Miscellaneous Device 1 Control (Dev1:0x40) Interrupt Pin Control This bit controls the IntPin field in AGP/PCI Interrupt and Bridge Control register (Dev1:0x3C). 0 = IntPin field is read-only. 1 = IntPin field is read-writable for BIOS initialization. Programming Notes 146 AMD-762TM System Controller Programmer's Interface Chapter 2 Preliminary Information 24462D--March 2002 AMD-762TM System Controller Software/BIOS Design Guide 2.5 Memory-Mapped Registers The AMD-762 system controller implements a set of memorymapped control registers as shown in Section 2.5.2 on page 149. Th e b a se fo r t h e s e reg is t e rs is d ef i n ed i n BA R 1 ( s ee "Dev0:F0:0x14" on page 39). This address is determined and loaded by system BIOS. The registers in the space are used by the AMD-762 system controller miniport driver to control the GART cache functionality during run time. 2.5.1 AMD-762TM System Controller GART Cache Overview This section provides a brief overview for programmers. The Graphics Address Relocation Table (GART) is a structure in memory that contains mappings from a virtual address generated by an AGP master (or any other master in the system including PCI masters and the CPU) and the actual physical address of a given request. The default mode used by the AMD-762 system controller GART cache is a two-level directory/table indexing scheme that is very similar to the standard x86 virtual memory architecture. By using two levels of indexing, the GART structure does not need to be physically contiguous. Figure 4 on page 148 illustrates the two-level indexing scheme. Chapter 2 AMD-762TM System Controller Programmer's Interface 147 Preliminary Information AMD-762TM System Controller Software/BIOS Design Guide 24462D--March 2002 AMD-762TM System Controller Physical Memory Northbridge 1K Table Entries Table Cache GART Table 1K Table Entries 16 Entries Fully Associative GART Directory Directory Entry 2 Directory Entry 1 Directory Cache 8 Entries Fully Associative GART Base Address register points here (Dev0:BAR1: 0x04). Figure 4. Two-Level GART Indexing 148 AMD-762TM System Controller Programmer's Interface Chapter 2 Preliminary Information 24462D--March 2002 AMD-762TM System Controller Software/BIOS Design Guide 2.5.2 Memory-Mapped Register Map For registers that are accessed by the AMD-762 system controller miniport driver during run time, the AMD-762 system controller implements a set of memory-mapped registers for quick access. These are defined in Table 16. Table 16. AMD-762TM System Controller Memory-Mapped Registers GART Memory-Mapped Control Registers Offset from BAR1 0x00 0x04 0x08 0x0C 0x10 Reference "Bar1 + 0x00" on page 150 "Bar1 + 0x04" on page 153 "Bar1 + 0x08" on page 154 "Bar1 + 0x0C" on page 155 "Bar1 + 0x10" on page 156 Feature Status Feature Control Capabilities Revision ID GART Base Address GART Cache Size GART Cache Control GART Cache Entry Control BAR1 Initialization Note that BIOS must program the Base Address 1:GART Memory Mapped Register Base register (Dev 0:F0:0x14) prior t o a c c e ss i n g t h e m e m o ry - m a p p e d re g i s t e rs . R e f e r t o "Dev0:F0:0x14" on page 39 for details of this register. Chapter 2 AMD-762TM System Controller Programmer's Interface 149 Preliminary Information AMD-762TM System Controller Software/BIOS Design Guide 24462D--March 2002 Features and Capabilities 31 Bit Reset R/W 23 Bit Reset R/W 15 Bit Reset R/W 7 Bit Reset R/W 0 0 0 0 R 6 0 0 R 5 4 Rev_ID 0 0 0 14 Reserved 0 0 0 0 22 Reserved 0 R 13 12 11 Hang_En 0 R/W 3 2 10 P2P_Cap 0 0 21 0 Reserved 0 30 29 28 27 P2P_Status 0 26 GART_Cache _Status 0 25 Bar1 + 0x00 24 Valid_Err 0 R/W1C 19 P2P_En 0 18 TLB_En 0 17 SB_STB_Tog _Det 0 R/W 9 Link_Cap 0 R 1 0 8 Valid_Cap 1 16 Gar_Valid_ Err_En 0 Valid_Bit_Err_ID 0 0 R 20 Reserved 0 1 Register Description 150 AMD-762TM System Controller Programmer's Interface Chapter 2 Preliminary Information 24462D--March 2002 AMD-762TM System Controller Software/BIOS Design Guide Bit Definitions Bit 31-30 29-28 Name Reserved Valid_Bit_Err_ID Function Reserved Features and Capabilities (Bar1 + 0x00) Valid Bit Error ID These bits are used to determine the source of the valid bit error. The values are as follow: 00 = AGP 01 = CPU 10 = PCI/AGP's PCI 11 = Reserved P2P Status This bit is hardwired to 0 to indicate that the AMD-762TM system controller implements only those PCI-to-PCI bridge commands required to implement AGP (the AMD-762 system controller does not implement a complete PCI 2.1-compliant PCI-to-PCI bridge between PCI and AGP). GART Cache Status 0 = GART cache disabled 1 = GART cache enabled by software Reserved Valid Bit Error When set, this bit indicates that a valid bit error has been detected and SERR# has been asserted. Refer to Table 7 on page 34 for details about SERR# assertion and status. This bit is cleared by writing a 1. Reserved P2P Enable This bit is hardwired to 0 to indicate that the AMD-762 system controller only implements those PCI-to-PCI bridge commands required to implement AGP (the AMD-762 system controller does not implement a complete PCI 2.1-compliant PCI-to-PCI bridge between PCI and AGP). TLB Enable When set, this bit enables the caching of GART TLB entries. Sideband Strobe Toggle Detect Disable When set, this bit disables the AGP sideband strobe toggle detect logic. GART Valid Error Enable When set, the AMD-762 system controller asserts SERR# when a graphics device attempts to access a page in AGP memory that is not valid (valid bit error). A valid bit error causes the GART table walk state machine to hang. The processor can still access memory after that if it does not use GART address space. Refer to Table 7 on page 34 for details about SERR# assertion and status. Reserved Hang Enable When set, illegal GART entries fetched by the GTW logic forces the AMD-762 system controller to hang. 27 P2P_Status 26 GART_Cache _Status Reserved Valid_Err 25 24 23-20 19 Reserved P2P_En 18 17 16 TLB_En SB_STB_Tog _Det_Dis GAR_Valid_Err _En 15-12 11 Reserved Hang_En Chapter 2 AMD-762TM System Controller Programmer's Interface 151 Preliminary Information AMD-762TM System Controller Software/BIOS Design Guide 24462D--March 2002 Bit Definitions (Continued) Bit 10 Name P2P_Cap Function Features and Capabilities (Bar1 + 0x00) P2PCap This bit is hardwired to 0 to indicate that the AMD-762TM system controller implements only those PCI-to-PCI bridge commands required to implement AGP (the AMD-762 system controller does not implement a complete PCI 2.1-compliant PCI-to-PCI bridge between PCI and AGP). LinkCap This bit is always Low, indicating that GART entry multiple pages are not supported. ValCap This bit is set to indicate that the AMD-762 system controller supports the detection of valid bit errors. Revision ID This field contains the revision identification. 9 8 Link_Cap Valid_Cap 7-0 Rev_ID Programming Notes 152 AMD-762TM System Controller Programmer's Interface Chapter 2 Preliminary Information 24462D--March 2002 AMD-762TM System Controller Software/BIOS Design Guide GART Directory Base Address 31 Bit Reset R/W 23 Bit Reset R/W 15 Bit Reset R/W 7 Bit Reset R/W 0 0 0 0 R 6 0 14 13 12 0 0 0 22 21 20 0 0 0 30 29 28 27 26 25 GART_Dir_Base_Addr 0 R/W 19 18 17 0 0 0 Bar1 + 0x04 24 0 16 GART_Dir_Base_Addr 0 R/W 11 10 Reserved 0 0 0 R 5 4 Reserved 0 0 0 0 3 2 1 0 0 0 9 8 0 0 0 0 GART_Dir_Base_Addr 0 R/W 0 Register Description Bit Definitions Bit 31-12 Name GART_Dir_Base _Addr Function GART Directory Base Address (Bar1 + 0x04) GART Directory Base Address These bits define the base address of the GART directory that is located in physical system memory. These 20 bits correspond to the 20 most significant bits of the 32-bit GART directory base address that is aligned on a 4-Kbyte page boundary. Twenty bits provide 4-Kbyte resolution, which is the minimum allowable size of the GART. A value other than 0 defines a valid base address. Reserved 11-0 Reserved Programming Notes Chapter 2 AMD-762TM System Controller Programmer's Interface 153 Preliminary Information AMD-762TM System Controller Software/BIOS Design Guide 24462D--March 2002 GART Cache Size 31 Bit Reset R/W 23 Bit Reset R/W 15 Bit Reset R/W 7 Bit Reset R/W 0 0 0 6 5 4 0 0 0 14 13 12 0 0 0 22 21 20 0 0 0 30 29 28 27 26 25 GART_Cache_Size 0 R 19 18 17 0 0 0 Bar1 + 0x08 24 0 16 GART_Cache_Size 0 R 11 10 9 8 0 0 0 0 GART_Cache_Size 0 R 3 2 1 0 0 0 0 0 GART_Cache_Size 1 R 0 0 0 0 Register Description Bit Definitions Bit 31-0 Name GART_Cache_Size Function GART Cache Size (Bar1 + 0x08) GART Cache Size The AMD-762TM system controller implements a GART table cache that contains 16 entries, organized as eight-way set associative. Programming Notes 154 AMD-762TM System Controller Programmer's Interface Chapter 2 Preliminary Information 24462D--March 2002 AMD-762TM System Controller Software/BIOS Design Guide GART Cache Control 31 Bit Reset R/W 23 Bit Reset R/W 15 Bit Reset R/W 7 Bit Reset R/W 0 0 0 6 5 4 Reserved 1 R 0 0 0 0 0 0 0 R 3 2 1 14 13 12 Reserved 0 0 0 0 0 0 0 R 11 10 9 22 21 20 Reserved 0 0 0 0 0 0 0 R 19 18 17 30 29 28 Reserved 0 0 0 27 26 25 Bar1 + 0x0C 24 0 16 0 8 0 0 GART_Cache _Inval 0 R/W1S Register Description Bit Definitions Bit 31-1 0 Name Reserved GART_Cache _Inval Function Reserved GART Cache Control (Bar1 + 0x0C) GART Cache Invalidate This bit is written by the AMD-762TM system controller miniport driver. When set to 1, the AMD-762 system controller invalidates the entire GART directory and table cache. When the invalidate operation is completed, the AMD-762 system controller resets this bit to 0. Programming Notes Chapter 2 AMD-762TM System Controller Programmer's Interface 155 Preliminary Information AMD-762TM System Controller Software/BIOS Design Guide 24462D--March 2002 GART Table Cache Entry Control 31 Bit Reset R/W 23 Bit Reset R/W 15 Bit Reset R/W 7 Bit Reset R/W 0 0 0 R 6 0 14 13 12 0 0 0 22 21 20 0 0 0 30 29 28 27 26 25 GART_Tbl_Entry_Addr 0 R/W 19 18 17 0 0 0 Bar1 + 0x10 24 0 16 GART_Tbl_Entry_Addr 0 R/W 11 10 Reserved 0 0 0 R 5 Reserved 0 0 0 4 3 2 1 Tbl_Update 0 R/W1S 0 Tbl_Inval _Entry 0 0 0 9 8 0 0 0 0 GART_Tbl_Entry_Addr 0 R/W 0 Register Description This register must be written to with doubleword (32-bit or 4-byte) operands. 156 AMD-762TM System Controller Programmer's Interface Chapter 2 Preliminary Information 24462D--March 2002 AMD-762TM System Controller Software/BIOS Design Guide Bit Definitions Bit 31-12 Name GART_Tbl_Entry _Addr Function GART Table Cache Entry Control (Bar1 + 0x10) GART Table Entry Address These bits define the page address for the particular GART table entry to be invalidated or updated. When a page address is written to this register by the Reserved miniport driver, the referenced GART table cache entry is invalidated or updated based on the value in bits [1:0] as long as it is within the virtual address space. If the page address is outside of the virtual address space, then the invalidate/update instructions do nothing. Reserved Table Update When set, this bit forces the AMD-762 system controller to update the GART table cache entry specified in bits [31:12] with the current entry in the GART table in system memory. The update function is performed immediately following the write to this register. When the update operation is completed, this bit is reset to 0. Table Invalidate Entry When set, this bit forces the AMD-762 system controller to invalidate the GART table cache entry specified in bits [31:12] if it is present in the GART cache. The invalidate function is performed immediately following the write to this register. When the invalidate operation is completed, this bit is reset to 0. Note that this bit does not affect the GART directory cache. 11-2 1 Reserved Tbl_Update 0 Tbl_Inval_Entry Programming Notes Chapter 2 AMD-762TM System Controller Programmer's Interface 157 Preliminary Information AMD-762TM System Controller Software/BIOS Design Guide 24462D--March 2002 158 AMD-762TM System Controller Programmer's Interface Chapter 2 Preliminary Information 24462D--March 2002 AMD-762TM System Controller Software/BIOS Design Guide 3 DDR SDRAM Interface This chapter details BIOS configuration as it pertains to the AMD-762TM system controller DDR SDRAM controller. The topics discussed in this chapter are entitled as follows: DDR DIMMS and DDR SDRAMs on page 160 * DDR Speed Grades on page 160 * DDR DIMM Data from Serial Presence Detect (SPD) Device on page 161 Memory Space Configuration on page 162 DDR Memory DIMM Timings on page 167 Additional Memory Controller Settings on page 171 DRAM Mode/Status Settings on page 174 ECC and Memory Scrubbing on page 178 Programmable Delay Lines (PDL) on page 183 DDR I/O Drive Strength on page 191 3.1 Overview To date, there are two types of DDR memory DIMMs-- unbuffered and registered. The AMD-762 system controller can be configured to support up to four registered DIMM slots with two banks each. The AMD-762 system controller embeds the DDR SDRAM memory controller of the system. All programming registers t h a t c o n f i g u re t h e m e m o ry c o n t ro l l e r re s i d e i n P C I configuration space. This space is defined in Bus 0, Device 0, and exists in both Function 0 and Function 1. Motherboard and Northbridge characteristics are programmed f ro m d a t a p rov i d e d by t h e re s p e c t ive d e s i g n e rs a n d manufacturers. This data includes bus speed implementations, memory bus signal strengths and slew rates, and internal memory controller characteristics, etc. Chapter 3 DDR SDRAM Interface 159 Preliminary Information AMD-762TM System Controller Software/BIOS Design Guide 24462D--March 2002 DI MM and me m ory dev ice ( m em ory chip) t im ing a nd configuration data exist in the Serial Presence Detect (SPD) EEPROM on the DIMM. 3.2 DDR DIMMS and DDR SDRAMs The following section discusses DDR DIMMS and DDR SDRAMS. 3.2.1 DDR Speed Grades DDR DIMMs adhere to an alternate naming convention associated with a corresponding data transfer rate. The data rate is a function of the clock speed of the memory subsystem, for example, 100-MHz clock or 133-MHz clock. Two names, and their corresponding transfer rates, are currently defined and implemented: PC1600 PC2100 The PC1600 naming convention represents DIMMs with a data transfer rate of 1600 Mbytes per second (1.6 Gbytes per second). This data rate is calculated as follows: PC1600 data transfer rate = (100-MHz clock) x (2 data transfers/clock) x (8 bytes/transfer) PC1600 data transfer rate = 1600 Mbytes per second Similarly, the PC2100 designation represents DIMMs with a data rate of 2100 Mbytes per second (2.1 Gbytes per second). This data transfer rate is calculated as follows: PC2100 data transfer rate = (133-MHz clock) x (2 data transfers/clock) x (8 bytes/transfer) PC2100 data transfer rate = 2100 Mbytes per second (rounded) Note that the CAS latency (CL) parameter of the device does not factor into the PC 1600 and PC2100 transfer rates calculated above. The CAS latency setting is dependent on device frequency, which is used in the calculation of the transfer rates above. The CAS latency values are DDR device160 DDR SDRAM Interface Chapter 3 Preliminary Information 24462D--March 2002 AMD-762TM System Controller Software/BIOS Design Guide specific and based on the operating frequency of the device. The CAS latency is specified as the initial latency (in clocks) required by the device before data is returned during a read access. In general, the higher the frequency, the larger the CAS latency value. Typical device CL parameters and their respective frequencies are shown in Table 17. Table 17. Typical CL Parameter Settings for PC1600 and PC2100 CAS Latency (CL) Setting 2 2.5 DDR Memory Clock Speed 100 MHz 133 MHz PC1600 PC2100 Designation Note: CAS latency settings are valid only if an acceptable entry for the corresponding bus speed exists in SPD byte 9 or 23. 3.2.2 DDR DIMM Data from Serial Presence Detect (SPD) Device DDR memory systems implemented with the AMD-762 system controller require use of the Serial Presence Detect (SPD) d a t a . T h i s d a t a d e s c r i b e s c o n f i g u ra t i o n a n d s p e e d characteristics of the DDR DIMM and DDR SDRAM devices mounted on the DIMM. The SPD is a serial EEPROM that physically exists on the DIMM and is encoded by the DIMM manufacturer. A description of this EEPROM is usually provided on a data sheet for the DIMM itself along with data describing the memory devices (chips) used. The data sheet should also contain the byte values for the DIMM encoded in the SPD on the DIMM. The SPD is accessed via the I2 C bus implemented on the motherboard, normally via registers in a Southbridge agent. Subroutines to access SPD data must be provided in the BIOS or other code that requires access. The I 2 C bus addresses the SPD via a 7-bit address where convention dictates that memory DIMMs respond to an address range beginning with 0xA0. The second memory DIMM responds to 0xA2 and so on. The I2C bus specification describes a 7-bit address. However, this scheme actually uses 8 bits. The 8th bit is actually bit 0. The scheme defines bit 0 as the read/write designation of the address. Bit 0 equal to 0 means that the host is executing a WRITE to the address. Bit 0 equal to 1 means that the host is executing a READ from the address. Reality then is that A1 addresses a read operation to DIMM slot #0. A3 addresses a Chapter 3 DDR SDRAM Interface 161 Preliminary Information AMD-762TM System Controller Software/BIOS Design Guide 24462D--March 2002 read operation to DIMM slot #1. A0 addresses a write operation to DIMM slot #0. 3.3 Memory Space Configuration A DIMM may have one or two sides populated with DDR devices. The term bank refers to one logical side of the DIMM memory. For the purpose of this document, each bank has a corresponding chip select. It is important to point out that double-sided DIMMs require two separate chip-select signals. Therefore, for these types of DIMMs, two separate base address chip-select registers must be programmed. The size of each bank is read from SPD, byte 31. The number of banks on the DIMM is read from SPD byte 5. The AMD-762 system controller DDR SDRAM controller requires 21 bits of configuration information for each chip select--that is, each side of the DIMM. These 21 bits are within a full 32-bit configuration register that contains 11 reserved bits. Usage of the 32 bits is shown in Table 18 and explained in further detail below. As previously mentioned, a DIMM socket may be single banked (containing one logical side of DDR SDRAM devices) or double banked (containing two logical sides of DDR SDRAM devices). The DIMM socket may also be empty. If one bank is not present or if the socket is empty--that is, two banks not present--then their corresponding enable bit shown in Table 18 should be set to 0. Table 18. DIMM Bank Address Bit Definition. Bit(s) 0 2:1 15:7 31:23 1 = Enable 0 = Disable Address Mode (modes 00 and 11 are reserved) Address Mask -- Size of this bank Base Address -- Starting address of this bank Bank n It is important that the registers place the largest logical bank of memory in the lowest address space and then progress in order to higher address space with the smaller sized banks. 162 DDR SDRAM Interface Chapter 3 Preliminary Information 24462D--March 2002 AMD-762TM System Controller Software/BIOS Design Guide When the DIMM socket sides are equally sized, the order of address space programming between them is not important. Each side/row/bank of DRAM requires 4 bytes as previously stated. The patterns that satisfy the Address Mask and Base Address for various sizes of sides/rows/banks are shown in Table 19. Table 19. Memory Size Addresses Bank / Row Size [Address Lines] 8 Mbytes 16 Mbytes 32 Mbytes 64 Mbytes 128 Mbytes 256 Mbytes 512 Mbytes 1024 Mbytes (1 Gbyte) 2048 Mbytes (2 Gbytes) N/A N/A 0000_0001_1 0000_0011_1 0000_0111_1 0000_1111_1 0001_1111_1 0011_1111_1 0111_1111_1 Address Mask [31:23] Base Address [31:23] 0000_0000_1 0000_0001_0 0000_0010_0 0000_0100_0 0000_1000_0 0001_0000_0 0010_0000_0 0100_0000_0 1000_0000_0 The address mask and base address bits are presented as xxxx_xxxx_x to show correspondence with address lines. In practice, the 9 bits of address mask map to bank n, bits 15:7 and the 9 bits of base address map to bank n, bits 31:23. The minimum memory size or granularity for DDR is 32 Mbytes. However, all base address and address mask bits represent a granularity of 8 Mbytes. The symmetry of the DDR device--that is, organization of storage elements rows and columns--dictates the addressing mode configuration. The specified addressing mode dictates the physical mapping of the memory address signals to the DDR device address signals. The addressing modes of the AMD-762 system controller memory controller map to industrystandard DDR device symmetries set forth by the Joint Electron Device Engineering Council (JEDEC). Therefore, the addressing mode is set according to the devices on the DIMM. Addr_Mode => 01b for 64-Mbit and 128-Mbit DRAMs Addr_Mode => 10b for 256-Mbit and 512-Mbit DRAMs DDR SDRAM Interface 163 Chapter 3 Preliminary Information AMD-762TM System Controller Software/BIOS Design Guide 24462D--March 2002 Note: Modes 00b and 11b are reserved. To determine the size of the DDR SDRAM device from SPD data, BIOS needs to read the size of the bank(s) in SPD byte 31 and the device width in byte 13. DDR SDRAM widths are either 4, 8, or 16 for this implementation. A 4-bit device width implies that 16 DDR SDRAM devices exist on a DIMM for a 64-bit bus transfer. An 8-bit device width implies eight DDR SDRAM devices exist on a DIMM for a 64-bit bus transfer, and a 16-bit width implies four DDR SDRAM devices exist on a DIMM for the 64-bit bus transfer. The size of the bank can be deduced as: Size of Device(Mbits) = Size of Bank x (SDRAM Width) where the Size of Device is specified in Mbits. Dividing the Size of Device value by eight (8) yields the size of the bank in Mbytes. If more than 4 Gbytes of total memory are populated in the system, it is the responsibility of BIOS to configure and report only 4 Gbytes to prevent a 4-Gbyte wrap, which would result in aliasing. Table 20 shows the total amount of memory with respect to DDR device density and width. Table 20. Total Memory Width and Density X16 128 Mbit X8 128 Mbit X4 128 Mbit X16 256 Mbit X8 256 Mbit X4 256 Mbit X16 512 Mbit X8 512 Mbit X4 512 Mbit DIMM 0 128 Mbytes 256 Mbytes 512 Mbytes 256 Mbytes 512 Mbytes 1 Gbyte 512 Mbytes 1 Gbyte 2 Gbytes DIMM 1 256 Mbytes 512 Mbytes 1 Gbytes 512 Mbytes 1 Gbytes 2 Gbytes 1 Gbytes 2 Gbytes 4 Gbytes DIMM 2 384 Mbytes 768 Mbytes 1.5 Gbytes 768 Mbytes 1 Gbytes 3 Gbytes 1.5 Gbytes 3 Gbytes DIMM 3 512 Mbytes 1 Gbytes 2 Gbytes 1 Gbytes 2 Gbytes 4 Gbytes 2 Gbytes 4 Gbytes Note: This table assumes double sided DIMMs. Note: Total system maximum is 4 Gbytes. Note: Shaded rows use x4 devices that are as registered DIMMs only. 164 DDR SDRAM Interface Chapter 3 Preliminary Information 24462D--March 2002 AMD-762TM System Controller Software/BIOS Design Guide This document assumes that BIOS uses the SPD to determine the total amount of memory in the system. This document does not specify a sizing algorithm other than utilizing the SPD. Base Address Chip Select The Base Address Chip Select bits (Dev 0:F0:0xC0, bits [31:23] through Dev 0:F0:0xDF, bits [31:23]) specify the 8-Mbytes boundary a given chip-select services. Each of the eight chip selects [7:0] have an associated Base Address Chip Select register. Incoming addresses are compared against the value programmed into the Base Address Chip Select register and also the Address Mask bits (Dev 0:F0:0xC0, bits [15:7] through Dev 0:F0:0xDF, bits [15:7]) of this register. The Address Mask bits (Dev 0:F0:0xC0, bits [15:7] through Dev 0:F0:0xDF, bits [15:7]) specify which address bits to ignore when incoming addresses are compared to the Base Address Chip Select bits Dev 0:F0:0xC0, bits [31:23] through Dev 0:F0:0xDF, bits [31:23]) defined in Base Address Chip Select. If a given bit is set in this register, its corresponding address bit in the address compare is ignored. The Address Mode bits (Dev 0:F0:0xC0, bits [2:1] through Dev 0:F0:0xDF, bits [2:1]) specify the memory address mapping. The address memory mapping is specific to the symmetry of the device and is shown in Table 21. As can be seen in this table, the maximum page width is 2 Kbytes. This maximum width implies that a new internal bank is accessed on a 2-Kbyte boundary. Note that address modes 00b and 11b are reserved, thus this field should never be specified. Address Mask Address Mode Table 21. Mode AMD-762TM System Controller DDR SDRAM Addressing Modes Pins Row Col 14 12 12 BK Row Col 12 12 BK 13 11 11 BK 11 11 BK 25 29 24 28 23 PC 22 27 21 26 20 10 19 9 18 8 17 7 16 6 15 5 14 4 13 3 12 11 24 27 10 23 PC 9 22 26 8 21 25 7 20 10 6 19 9 5 18 8 4 17 7 3 16 6 2 15 5 1 14 4 0 13 3 Mode 1 Addr_Mode=01 64Mb x4/8/16 128Mb x4/8/16 Mode 2 Addr_Mode=10 256Mb x4/8/16 512Mb x4/8/16 Chapter 3 DDR SDRAM Interface 165 Preliminary Information AMD-762TM System Controller Software/BIOS Design Guide 24462D--March 2002 Chip Select Enable The Chip Select Enable bit (Dev 0:F0:0xC0, bit [0] through Dev 0:F0:0xDF, bit [0]) specifies whether a bank of memory exists for that corresponding chip select. When enabled with a 1b, the incoming address is eligible to be compared with bits [31:23] and [15:7] for chip-select decode. A 0b in this field disables the associated chip select, thus the associated Base Address Chip Select and Address Mask fields are ignored. Table 22 is an example of how to size the Memory Base register for a total of 128 Mbytes using a two-bank DIMM at 64 Mbytes per bank. Table 22. Memory Sizing Example, 128 Mbytes Total Registers - Bus:00 Device:00 Function:00 0 1 2 3 4 5 6 7 8 9 A B C D E F C 83 03 00 00 83 03 00 04 00 00 00 00 00 00 00 00 D 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Example: Memory Base Address Registers For the purpose of illustrating memory sizing, the bytes 0xC0- 0xDF are the relevant bytes. Configuration bytes C0h, C1h, C2h, and C3h are for Bank 0. Byte C0h contains bits [7:0], C1h bits [15:8], etc. This example shows 64 Mbytes in both banks 0. Configuration bytes C4h, C5h, C6h, and C7h are for bank 1 Bits C0h[7] and C1h[7:0] contain the Address Mask for 64 Mbytes. Bits C4h[7] and C5h[7:0] contain the Address Mask for 64 Mbytes. Bit C0h[0] and bit C4h[0] signal Bank Enable. Bit C2h[7] and bits C3h[7:0] set a Base Address of 0 Mbyte for side/row/bank 0. Bit C6h[7] and bits C7h[7:0] set a Base Address of 64 Mbytes for side/row/bank 1. The total memory size is 128 Mbytes. Banks 2-7 are empty. The relevant bytes are set to 0. 166 DDR SDRAM Interface Chapter 3 Preliminary Information 24462D--March 2002 AMD-762TM System Controller Software/BIOS Design Guide Table 23 is an example on how to size the Memory Base register for a total of 320 Mbytes using one-bank DIMM at 64 Mbytes per bank and a two-bank DIMM at 128 Mbytes per bank. Table 23. Memory Sizing Example, 320 Mbytes Total Registers - Bus:00 Device:00 Function:00 0 1 2 3 4 5 6 7 8 9 A B C D E F C 83 03 00 10 00 00 00 00 83 07 00 00 83 07 00 08 D 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 3.4 DDR Memory DIMM Timings One of the most important changes from earlier SDRAM DIMM technology is that conservative settings for CAS Latency (CL) are no longer valid--that is, when there is doubt that the DIMM works using CL=2, falling back to a setting of CL=3 is not an alternative as it was on single data rate devices. CAS latency for a DIMM must be set to a value described in the SPD on the DIMM. A DIMM that is set to something other than a rated value in its SPD cannot be expected to work and most likely will not work. Industry standards for CL on DDR DIMMS are 1.5, 2.0, and 2.5. Please notice that the AMD-762TM system controller supports CL=3.0 as the highest CL setting. Some legacy DDR devices support CL=3.0, but most devices available today specify CL=2.5 as a maximum. The AMD-762 system controller does not support CL=1.5. 3.4.1 Memory Timings The AMD-762 system controller supports the following DDR device timing parameters: tCL, tRCD, tRAS, tRP, tRC, tRRD, tWR, and tWTR. The tCL, tRCD, tRAS, tRP, tRC, and tRRD timings are available from the SPD. The data format of each byte is described in the application note published by IBM and other sources. Matching this data to memory controller settings is a function of speed of the memory bus. Examples of settings are developed for bus speeds of 100 MHz and 133 MHz. Chapter 3 DDR SDRAM Interface 167 Preliminary Information AMD-762TM System Controller Software/BIOS Design Guide 24462D--March 2002 CAS Latency CAS latency values can occupy multiple bytes in the SPD. CAS latency is the only item governing DIMM setup that has multiple values. Table 24 shows CAS latency settings. Table 24. CAS Latency Settings Symbol Name SPD Byte Typical Value Description Max bus speed for CL=2.5 with AMD-762TM system controller. 0 9 75h DIMM does not support CL=2.5. 75h equal 7.5 ns. This DIMM can be used @ CL = 2.5 when bus speed is less than or equal to 133 MHz. A0h equals 10 ns. This DIMM can be used @ CL = 2.5 when bus speed is less than or equal to 100 MHz. Max bus speed for CL=2 with AMD-762TM system controller. 0 23 75h DIMM does not support CL=2. 75h equal 7.5 ns. This DIMM can be used @ CL = 2 when bus speed is less than or equal to 133 MHz. A0h equals 10 ns. This DIMM can be used @ CL = 2 when bus speed is less than or equal to 100 MHz. A0h tCL CAS Latency 0x0x0x54[3:2] A0h Notes: 1. Other values in byte 9 represent other maximum bus speeds for CL=2.5. Should another speed occur, CL=2.5 cannot be used beyond its max for this DIMM--that is, byte 9 = 80 means a maximum bus speed of 120 MHz. CL=2.5 can be used for a maximum bus speed of 100 MHz, but not for 133 MHz. 2. Other values in byte 23 represent other maximum bus speeds for CL=2. Should another speed occur, CL=2 cannot be used beyond its max for this DIMM--that is, byte 23 = 80 means a maximum bus speed of 120 MHz. CL=2 can be used for a maximum bus speed of 100 MHz, but not for 133 MHz. The two entries for supported CAS latency(CL) represent different performance potential. The smaller value for CL (2) would represent best performance. BIOS can choose from any legal CL that exists in the SPD for the DIMM. The AMD-762 system controller supports CL values of 2, 2.5, and 3. Other timing values in the SPD reflect minimum timings required, based on the corresponding memory bus clock speed. BIOS must program the memory controller configuration with the correct timing values as specified by the DDR device. 168 DDR SDRAM Interface Chapter 3 Preliminary Information 24462D--March 2002 AMD-762TM System Controller Software/BIOS Design Guide tRCD The RAS to CAS delay bits (Dev 0:F0:0x54, bits [1:0]) specify the minimum amount of time required between the opening of a page within the DDR device (via an ACTIVATE command) and the issuance of a READ or WRITE command to that same DDR device's internal bank. This timing parameter is devicespecific. Byte 29 of the SPD defines the tRCD timing parameter. Refer to Table 25 on page 170 for typical settings. The Row Active bits (Dev 0:F0:0x54, bits [6:4]) specify the minimum amount of time that a page within the DDR device (via an ACTIVATE command) can remain opened within the same internal bank of the DDR device. This timing parameter is device-specific. Byte 30 of the SPD defines the tRAS timing parameter. Refer to Table 25 on page 170 for typical settings. The Row Precharge time bits (Dev 0:F0:0x54, bits [8:7]) specify the minimum amount of time that the DDR device requires to precharge a row and is specified as the time between the PRECHARGE command and an ACTIVATE command within the same internal bank of the DDR device. This timing parameter is DDR device-specific. Byte 27 of the SPD defines the t RP timing parameter. Refer to Table 25 on page 170 for typical settings. The Row Cycle time bits (Dev 0:F0:0x54, bits [11:9]) specify the minimum amount of time that the DDR device requires between ACTIVATE commands within the same internal bank of the DDR device. This timing parameter is DDR devicespecific. In short, this requirement specifies the minimum amount of time that the same internal bank can recycle row accesses. Byte 41 of the SPD defines the tRC timing parameter. (Note that tRC is new to the SPD and voted in at the September 2000 JEDEC meeting.) Historically, tRC was defined as tRAS + t RP, but this algorithm is not recommended when the SPD information is available. Refer to Table 25 on page 170 for typical settings. The Bank to Bank ACTIVATE time bit (Dev 0:F0:0x54, bit [23]) specifies the minimum amount of time that the same DDR device can receive back-to-back ACTIVATE commands, even to different internal banks. This timing parameter is DDR devicespecific. Device manufacturers specify the tRRD parameter to limit current surges within the device, based on row ACTIVATE activity, because row activates require a large amount of tRAS tRP tRC tRRD Chapter 3 DDR SDRAM Interface 169 Preliminary Information AMD-762TM System Controller Software/BIOS Design Guide 24462D--March 2002 current. Byte 28 of the SPD defines the tRRD timing parameter. Refer to Table 25 on page 170 for typical settings. Write Recovery The Write Recovery bits (Dev 0:F0:0x54, bit [25:24]) specify the minimum amount of time that must occur from the last WRITE command to a PRECHARGE command to the same internal bank of the DDR device. This device timing parameter is not specified in the SPD, but the recommended setting is 10b and specifies two system clock cycles between a write command and a precharge command to the same internal bank. Refer to Table 25 on page 170 for typical settings. The Write To Read bit (Dev 0:F0:0x54, bit [26]) specifies the minimum amount of time that must occur between the last WRITE command to a following READ command to the same internal bank of the DDR device. This device timing parameter is not specified in the SPD, but the recommended setting is 1b and specifies two system clock cycles. Refer to Table 25 on page 170 for typical settings. Table 25. Symbol Write to Read DDR Device Timing Values Name Minimum RAS to CAS Delay 0x0x0x54[1:0] Minimum Active to Precharge Time 0x0x0x54[6:4] Minimum Row Precharge Time 0x0x0x54[8:7] Bank Cycle Time 0x0x0x54[11:9] Minimum Row Active to Row Active Delay 0x0x0x54[23] Minimum Write to Precharge Time Minimum Write to Read Time SPD Typical Value Byte 29 50h Description Has 2-bit fraction--see SPD definitions. 50h = 20 ns. 2 cycles @100 MHz, 3 @ 133 MHz. Integer value. 50-ns requirement. 5 cycles @ 100 MHz, 7 @ 133 MHz. Has 2-bit fraction--see SPD definitions. 50h = 20 ns. 2 cycles @100 MHz, 3 @ 133 MHz. Typically defined as tRAS + tRP. SPD entry available soon. 7 cycles @ 100 MHz, 10 @133 MHz. Has 2-bit fraction--see SPD definitions. 3Ch = 15 ns. 2 cycles @100 MHz and 133 MHz. tRCD tRAS 30 32h tRP 27 50h tRC 41 tRRD tWR tWTR 28 N/A N/A 3Ch N/A N/A 170 DDR SDRAM Interface Chapter 3 Preliminary Information 24462D--March 2002 AMD-762TM System Controller Software/BIOS Design Guide Example configurations are shown in Table 26. Table 26. CL 2 2.5 Dev 0:F0:0x54 Bit Examples DIMM 100 MHz Registered 133 MHz Registered Dev 0:F0:0x54 57 56 55 54 7E 01 88 B5 F6 01 8E 5A 3.5 Additional Memory Controller Settings This section discusses configuration features that are specific to the AMD-762 system controller DDR memory controller. The AMD-762 memory controller contains DDR memory controller settings starting at (Dev 0:F0:0x54). These settings are Page Hit Limit, Idle Cycle Limit, Registered DIMM Enable device control (used in this register to specify registered versus unbuffered DIMM), Read Wait State timing control, selectable HOLD time for t he DDR address a nd comma nd buse s (selectable per address and command bus A and B), and a selectable wait state for Super Bypass control. Page Hit Limit The Page Hit Limit bits (Dev 0:F0:0x54, bits [15:14]) specify the number of consecutive Page Hit requests that are processed by the AMD-762 DRAM controller before choosing a non-page hit request. This feature is designed to reduce starvation (a pending request not fulfilled for an extended period of time) due to a flood of consecutive page hit requests. Typically, consecutive page hits yield the best DDR DRAM page performance for those requesting devices (such as the CPU or PCI device, etc.). However, starvation of a request because it is a non-page-hit request does not constitute a fair system memory access policy. When the number of consecutive page hits across all internal DDR device internal banks of a given chip select equals the value specified in these bits, the DDR controller arbiter gives priority to a DDR memory request that is not a page hit. It was determined that eight consecutive page hit accesses is adequate to give fair access to the memory sub-system. Therefore, these bits should be set to 10b. A higher page hit limit allows the prioritization of a large amount of consecutive Chapter 3 DDR SDRAM Interface 171 Preliminary Information AMD-762TM System Controller Software/BIOS Design Guide 24462D--March 2002 page hits, if available, whereas a lower page hit limit would allow for a greater chance of page interruption should there be an otherwise large amount of page hit requests. Refer to Table 27 on page 174 for typical settings. Idle Cycle Limit The Idle Cycle Limit bits (Dev 0:F0:0x54, bits [18:16]) specify the number of system clocks before the memory controller issues a PRECHARGE ALL command to the currently active chip select. This feature is used to tune system performance by closing open pages during periods of memory request inactivity. The idle cycle limit logic does not have any logical indication of page conflicts or bank misses and simply counts the number of system clocks of memory request inactivity. This feature takes advantage of the lack of temporal locality, where a page left open for a specified amount of time is less likely to be accessed again. Therefore, it is more advantageous to precharge the page and incur the page miss overhead rather than the overhead associated with a page conflict. Analysis shows that eight idle clocks is an adequate amount of system clocks to wait for a following request to the memory sub-system. Therefore, these bits should be set to 001b for best performance. A higher idle cycle limit allows a greater chance for a following request to access an open page. However, temporal locality states that the greater amount of time between accesses reduces the chance of a hit to the open page. A lower idle cycle limit decreases the window of following memory access to utilize an open page. A lower idle cycle limit results in a greater chance of page interruption should there be an otherwise large amount of page hit requests. Refer to Table 27 on page 174 for typical settings. Registered DIMM Enable The Registered DIMM Enable bit (Dev 0:F0:0x54, bits [27]) specifies whether the DDR DIMM sockets are populated with registered or unbuffered DIMM modules. This bit must be set to 1b by BIOS. Refer to Table 27 on page 174 for typical settings. The Read Wait State bit (Dev 0:F0:0x54, bits [28]) specifies whether more time is needed in the DDR read data round trip loop. The read data round trip loop originates at the AMD-762 system controller DDR CLK outputs and terminates at the AMD-762 system controller internal requester logic. Because all DDR read data is returned with its corresponding DQS signal, read data is captured at the memory controller interface DDR SDRAM Interface Chapter 3 Read Wait State 172 Preliminary Information 24462D--March 2002 AMD-762TM System Controller Software/BIOS Design Guide in the DQS clock domain. This data is then held and crosses into the core requester clock domain. However, because of the physical DIMM placement on the motherboard, large round trip delays the response time of the DDR devices, and AMD-762 system controller internal delays may be long enough that an additional wait state must be added to compensate for the delay. When this bit is set to a 1b, the data captured in the DQS clock domain is transferred to a register array that is within the core logic clock domain and physically exists at the pads of the AMD-762 system controller DDR interface. When this bit is set to a 1b, the data is delayed to the requester by one additional system clock period. Because the Read Wait State bit is related to the full read data round trip and may imply that the read data and DQS are being returned from a far DIMM, when the Read Wait State bit is set to 1b, one additional clock cycle is placed between READ followed by WRITE cycles to prevent data and DQS overlap when accessing a far DIMM for read data and followed immediately by a write cycle. Because of motherboard timing analysis and AMD-762 system controller timing analysis, it is recommended that this bit be set for 100-MHz and 133-MHz operation. Refer to Table 27 on page 174 for typical settings. Address Timing for Copy-B The address timing for Copy-B bit (Dev 0:F0:0x54, bit [29]) specifies additional HOLD time for the address and command bus B. When this bit is set to 1b, the memory address bus (MAB[14:0]), RASB#, CASB#, WEB#, CKEB, and CS[7:6 and 3:2]# is delayed an additional 350 ps (best case) and 600 ps (worst case) to provide additional HOLD time to the DDR device. This bit should be set by BIOS. This bit assumes A bus and B chip-select DIMM socket mapping is such that the B bus uses Chip Select bit [7:6] and [3:2]. This motherboard mapping should be adhered to should BIOS want to control the A bus and B bus HOLD timing separately. Refer to Table 27 on page 174 for typical settings. Address Timing for Copy-A The address timing for Copy-A bit (Dev 0:F0:0x54, bit [30]) specifies additional HOLD time for the address and command bus A. When this bit is set to 1b, the memory address bus (MAA[14:0]), RASA#, CASA#, WEA#, CKEA, and CS[5:4 and 1:0]# is delayed an additional 350 ps (best case) and 600 ps DDR SDRAM Interface 173 Chapter 3 Preliminary Information AMD-762TM System Controller Software/BIOS Design Guide 24462D--March 2002 (worst case) to provide additional HOLD time to the DDR device. This bit should be set by BIOS. This bit assumes A bus and B chip-select DIMM socket mapping is such that the B bus uses Chip Select bit [5:4] and [1:0]. This motherboard mapping should be adhered to should BIOS want to control the A bus and B bus HOLD timing separately. Refer to Table 27 on page 174 for typical settings. Super Bypass Wait State The Super Bypass Wait State bit (Dev 0:F0:0x54, bit [31]) specifies an additional one system clock wait state for super bypass requests, when set to 1b. A super bypass cycle is a lowlatency request to DDR memory from the bus interface unit when all reordering queues are empty. This super bypass cycle allows direct access to DDR memory. For internal timing reasons, this bit must be set for 133-MHz operation. This bit should be set to 0b for 100-MHz operation or below. Refer to Table 27 for typical settings. Table 27. System Related Timings Name Page Hit Limit Idle Cycle Limit Registered DIMM Enable Read Wait State Address Timing for Copy-B Address Timing for Copy-A Super Bypass Wait State 0x0x0x54 Bit(s) Typical Setting 15:14 18:16 27 28 29 30 31 10b 001b 1 1 1 1 X Description 8 cycles 8 cycles 1 for registered Always set 1 for registered 1 for registered 0 < 133 MHz 1 @ 133 MHz 3.6 DRAM Mode/Status Settings The AMD-762 system controller memory controller contains additional DDR memory controller settings starting at (Dev 0:F0:0x58). These settings are: x4 DDR device symmetry configuration, refresh control (which includes refresh rate, refresh disable, and burst refresh enable), suspend to RAM (STR) control, DDR device initialization control, and AMD-762 system controller DDR clock output control. 174 DDR SDRAM Interface Chapter 3 Preliminary Information 24462D--March 2002 AMD-762TM System Controller Software/BIOS Design Guide Chip-Select Width The SDRAM Chip-Select Width bits (Dev 0:F0:0x58, bits [7:0]) are used to indicate DDR device data widths installed for the corresponding chip select. The AMD-762 system controller can differentiate between x4 or x8/x16 banks by BIOS setting a corresponding bit for the chip select in this register. A bit should be set to 1b to represent a x4 bank or set to 0b to represent a x8/x16 bank. The x8 and X16 devices use one DQS data strobe per byte, whereas a x4 device uses one DQS data strobe per nibble (4-bit). Because the AMD-762 system controller DRAM controller uses the data mask (DM) signals as DQS data strobes during data transfers to x4 devices, the DRAM controller uses these bits to determine the function for the DM signals. The AMD-762 system controller provides a data width selection for each chip select, although it is unlikely that a double banked DIMM can support x4 devices on one side and x8/x16 devices on the other. However, this resolution is provided to allow chipselect signal routing flexibility on the motherboard should the same DIMM socket not use neighboring chip-select wiring. The SPD byte 13 provides DDR device data width information and can be used to set these bits accordingly. SDRAM Initialization The SDRAM Initialization bit (Dev 0:F0:0x58, bit [25]), when written to a 1b, initiates the DDR device initialization sequence. However, as mentioned below, the Suspend to RAM bits (Dev 0:F0:0x58, bits [22:21]) must be written to a 01b in order for the initialization sequence to occur. The BIOS should first initialize the DDR timing control registers and drive strength registers prior to setting this bit. This bit remains set after the initialization sequence has completed. Status as to the completion of the initialization sequence can be provided by polling the Mode Register Status (Dev 0:F0:0x58, bit [23]) but only after setting the Mode Register Status bit. This procedure is described below. The SDRAM Initialization bit is reset to 0b during a Suspend To RAM because a system reset is issued in this case. The Mode Register bit (Dev 0:F0:0x58, bit [23]), when written with a 1b, is used to initiate a Load Mode Register command to the DDR devices. The Load Mode Register command programs the CAS latency of the device, burst length, and burst order. The burst length and burst order are fixed to a burst of eight and the device is programmed for interleaved mode. However, DDR SDRAM Interface 175 Mode Register Status Chapter 3 Preliminary Information AMD-762TM System Controller Software/BIOS Design Guide 24462D--March 2002 the CAS latency is configurable via the CAS Latency bit. BIOS must set the CAS latency bit to its correct value (defined by DDR devices specification and operating frequency) before the Mode Register bit is set. This bit is then cleared by the AMD-762 system controller memory controller after the load mode register cycle is issued to the DDR devices. Therefore, after setting this bit, BIOS should poll this bit until it becomes 0b to verify that the Load Mode Register command has been a p p l i e d t o t h e D D R d ev i c e s b e fo re c o n t i nu i n g . T h e recommended method is to set this bit (after already initializing the CAS Latency bit) when writing to this register to set bits [22:21] of this register to a 01b and bit 25 of this register to a 1b. Because the DDR initialization has priority over the application of the Load Mode Register command and the Load Mode Register command is the last command applied in the DDR initialization, this bit can be polled to prove status as to when the entire DDR initialization is complete. Suspend to Ram Control The Suspend to RAM bits (Dev 0:F0:0x58, bits [22:21]) are used by BIOS to communicate the power-up sequence to the AMD-762 system controller. The BIOS usage of the Suspend to RAM control bits are defined in the power management section (see Section 4.3.1 on page 198). Burst Refresh Enable The Burst Refresh bit (Dev 0:F0:0x58, bit [20]) allows the AMD-762 system controller to skip refreshes that are queued, until the maximum number (four) is reached. Burst refresh support is a performance enhancement that prevents refresh requests from interfering with memory requests. Refresh requests that would have interfered with memory requests would normally stall the memory accesses or interfere with the open page policy by prematurely closing pages due to the refresh. When burst refresh is enabled and the burst queue is beginning to fill up, the DRAM controller treats the refresh queue requests as an urgent priority. Refresh Disable The Refresh Disable bit (Dev 0:F0:0x58, bit [19]) allows the disabling of refresh cycles for debug purposes only. This bit is not reset during a system reset and it is therefore the responsibility of BIOS to write this bit to a 0 to enable refresh cycles. 176 DDR SDRAM Interface Chapter 3 Preliminary Information 24462D--March 2002 AMD-762TM System Controller Software/BIOS Design Guide Cycles per Refresh The Cycles per Refresh bits (Dev 0:F0:0x58, bits [17:16]) provide a setting to specify the DDR refresh rate. The refresh rate is tied directly to the clock frequency, thus it is important for BIOS to configure the refresh rate based on the AMD-762 system controller frequency. BIOS should first determine the AMD-762 system controller operating frequency by reading (Dev 0:F0:0x58, bits [21:20]) and setting these bits according to Table 28 below. The refresh rate should not be configured slower than that specified by any of the DDR devices installed. ( E a ch D I M M i n s t a l l e d m ay h ave a d i f f e re n t re f re s h requirement, so it is important to choose the refresh rate that satisfies the least common denominator for all DIMMs.) Table 28. Value Refresh Rate 66 MHz 100 MHz 133 MHz 00 01 10 11 DIMM Clock Disable 30.72 s 23.04 s 15.36 s 7.68 s 20.48 s 15.36 s 10.24 s 7.68 s 15.36 s 11.52 s 7.68 s 3.84 s The DIMM clock disable bits (Dev 0:F0:0x58, bits [31:26]) provide a way to individually disable the six differential DDR clock pairs provided for the DDR DIMMs. After BIOS memory sizing, these bits can be used to disable clocks to empty DDR DIMM slots. The setting of a bit disables the corresponding clock pair. Each clock pair is connected according to the motherboard layout for registered DIMMs. Refer to the appropriate motherboard schematic to verify DDR clock DIMM mapping to a particular DIMM slot. With a system hard reset, these bits are cleared, thus enabling all clock pairs. Because an AMD-762 system controller system reset is issued during a power-managed S3 state, all clocks are re-enabled following the exit from this state. Therefore, BIOS should return to this register and restore the disabled clock pairs that it had previously disabled during POST. Chapter 3 DDR SDRAM Interface 177 Preliminary Information AMD-762TM System Controller Software/BIOS Design Guide 24462D--March 2002 3.7 ECC and Memory Scrubbing The AMD-762 system controller DDR SDRAM controller supports error correcting code (ECC) and memory scrubbing. The error correction capability allows the correction of singlebit errors and the detection of multiple-bit errors in any memory quadword. Data is only checked by the memory controller during a read access. A data error may be due to a faulted bit in the DDR device itself, or a faulted bit that occurred during data transmissions from the DDR devices to the AMD-762 system controller memory controller. To support the ECC function, DIMMs must support additional storage for the ECC check bits. When ECC is enabled, the system must have all DDR DIMMs that are 72 bits wide (also called ECC DDR DIMMs). The AMD-762 system controller DDR SDRAM controller provides five ECC modes. The five modes supported are: ECC Disabled High-Performance EC Mode (EC_HiPerf mode)--Error Checking only, no correction, except to the AMD AthlonTM processor High-Performance ECC Mode (ECC_HiPerf mode)--Error Checking and Correction ECC with Scrubbing (ECC_Scrub mode)--Error Checking and Correction with Scrubbing Diagnostic ECC mode (ECC_Diag) Each mode is discussed below. The ECC check bits that are stored in the additional DDR devices on the DIMM are generated by the memory controller (based on a Hamming code algorithm) and written into the DIMMs check bit storage during a memory write operation when any ECC function is enabled. A single byte of check bits represents the associated quadword of data that is written into memory. Whe n any ECC m o d e is en able d a n d a re ad a c c es s i s performed, the memory controller internally generates check bits based on the data value read (for each quadword of data read) and compares it with the check bits read along with the data from the check bit storage of the DIMMs. If the generated 178 DDR SDRAM Interface Chapter 3 Preliminary Information 24462D--March 2002 AMD-762TM System Controller Software/BIOS Design Guide value does not match the check bit value, then both values are used to detect the number of bits that contain errors and the bit positions that contain errors. If only a single-bit error is detected, the generated check bits and the read check bits are used to correct the bit and pass the corrected data back to the requester that requested the read data. This single-bit error is signalled for system status. A read requester may be either the AMD AthlonTM processor, PCI, AGP, APC, or GART. The detection of more than a single-bit error signals a multiple-bit system error and this data is not corrected. When any of the AMD-762TM system controller ECC features are enabled, all DDR DIMMs installed must support ECC and all memory locations must be written to (initialized) prior to system operation to generate check bit values that match the data written for every location of memory. It is the responsibility of the BIOS to initialize all memory locations prior to any ECC function being enabled. The additional logic to support the ECC function is costly in both silicon real estate and system timing. In the ECC modes that support data correction, one additional system clock must be used to generate the corrected data. However, because the AMD Athlon processor checks for its own errors, data is passed directly through the AMD-762 system controller without an additional system clock delay. The detailed implementation of error detection and correction differs dependent on whether the read or write is from the processor or PCI, APC, AGP, or GART and whether the write is a full quadword or less than a full quadword in size. The processor generates ECC for all full quadword writes and checks and corrects (if necessary) on all reads. For processor, PCI, APC, AGP, or GART partial quadword writes, the memory system performs a read-modify-write operation by reading the existing memory location, correcting the memory data if necessary, merging in the modified bytes, generating new ECC, and writing the new value to memory. A read-modify-write operation is used only for all partial quadword writes. The data read from memory during a read-modify-write operation is checked and corrected before the merge/write operation. A detailed operation is further described in Table 29 on page 180. Chapter 3 DDR SDRAM Interface 179 Preliminary Information AMD-762TM System Controller Software/BIOS Design Guide 24462D--March 2002 Table 29. AMD-762TM System Controller ECC Behavior (with ECC Enabled) Operation ECC Generated By: DRAM AMD Athlon Processor AMD-762 System Controller RMW on each QW DRAM AMD-762 System Controller AMD-762 System Controller RMW on each QW ECC Checked By: AMD-762TM System Controller and AMD Athlon Processor None SBEs1 Corrected By: AMD Athlon Processor None AMD AthlonTM Processor System Bus Read AMD Athlon Processor System Bus Full Quadword Writes AMD Athlon Processor System Bus Partial Quadword Writes PCI/APCI/GART3 Read PCI/APCI/GART3 Full Quadword Writes PCI/APCI/GART3 Partial Quadword Writes AMD-762 System AMD-762 System Controller2 Controller2 AMD-762 System AMD-762 System Controller Controller None None AMD-762 System AMD-762 System Controller2 Controller2 Notes: 1. Single-bit error (SBE). 2. The data read from memory is checked and corrected before the merge/write. 3. APCI =Alternate PCI on AGP interface. 4. The scrubbing circuit detects, corrects read errors, and writes the corrected data to memory. Memory scrubbing not only corrects single-bit errors to the requesters and detects multiple-bit errors, but also writes the corrected single-bit error value back into memory when this feature is enabled. Refer to "ECC_Mode" on page 181 for more information regarding the memory scrubbing feature and configuration. In addition to the status bits and chip-select identification, the AMD-762 system controller allows single-bit and/or multiplebit errors to optionally assert SERR# to allow monitoring, logging, and analysis of ECC errors by software. SysECCEn bit should be set in the AMD Athlon processor when setting "Report ECC Syndrome case." SysECCEn has an MSR address of MSR C001_0010[15]. 180 DDR SDRAM Interface Chapter 3 Preliminary Information 24462D--March 2002 AMD-762TM System Controller Software/BIOS Design Guide 3.7.1 SERR_Enable ECC and Memory Scrubbing Configuration The System Error Enable bits (Dev 0:F0:0x48, bits [15:14]) control the AMD-762 system controller reporting of ECC errors to the system via the SERR# pin on the PCI bus. Note that SERR# assertion is still subject to the normal PCI SERR# Enable (Dev 0:F0:0x04, bit [8]). Error reporting options are as follow: 00 = SERR# assertion disabled X1 = Multiple bit errors force SERR# assertion 1X = Single bit errors force SERR# assertion ECC_Diag The Error Correcting Code Diagnostic Mode Enable (Dev 0:F0:0x48, bit [12]) provides a way to purposely corrupt the ECC check bits. When this mode is enabled, the AMD-762 system controller always writes 0x00h to the ECC check bit byte. During partial writes, the RMW sequence still occurs, but the ECC bits are always written to 0x00. This bit is useful for logic testing and ECC driver development. A check bit value of 0x00 is a valid check bit code, so care should be used to not corrupt a location where the user does not expect this valid check bit value to exist. In the ECC_Diag mode, the AMD-762 system controller always writes 0x00 to the ECC byte to aid testing of the ECC logic. For reads, the ECC circuitry is unaffected by the ECC_Diag bit. The ECC code returned from memory is checked, and errors are reported in the ECC_Status bits as usual. Correction is not performed in this mode to PCI, AGP, APC, or GART. However, as mentioned earlier, because the AMD-762 system controller simply passes ECC and read data information directly to the AMD Athlon processor, the processor may correct this data if this feature is enabled in the processor. ECC_Mode The Error Correcting Code mode bits enable a specific ECC mode. These fields can be used in the following cases: Disable ECC checking. In this mode, ECC is neither generated nor maintained in the memory, and correction is not performed. This mode is intended for memory systems that are only 64 bits in width. Enable ECC error checking mode only where data is still checked and errors are still reported, but data destined for the PCI or APCI/GART is not corrected. This approach DDR SDRAM Interface 181 Chapter 3 Preliminary Information AMD-762TM System Controller Software/BIOS Design Guide 24462D--March 2002 provides the benefit of detecting an error but does not incur the one clock penalty that is necessary for data correction for data destined for the PCI or AGP. Data and ECC check bits are still passed from the DDR devices to the AMD Athlon processor, which performs its own data error detection and correction. Therefore, data correction to the AMD Athlon processor is not inhibited in this mode. This mode provides all the benefits of parity checking with little or no performance impact. It is useful in systems that desire status information but not the overhead that is associated with error correcting or scrubbing. A system can transition between the EC_HiPerf mode, ECC_HiPerf mode, and ECC_Scrub mode dynamically, thereby getting the desired benefits of each mode as needed. Enable ECC error checking and correction mode. Data destined for the PCI or APCI/GART is corrected but at the expense of one clock cycle. As always, data and ECC check bits are still passed from the DDR devices to the AMD Athlon processor, which performs its own data error detection. The AMD-762 system controller provides a highperformance ECC mode (ECC_HiPerf) that provides all the data integrity benefits of ECC but without the overhead of scrubbing. In this mode, ECC is written into memory during writes (partial writes result in a RMW sequence), and correction is performed on reads. ECC checking is performed and the status indicators provide valid information regarding errors. This mode is useful in systems that need status information and data integrity but not the overhead that is associated with scrubbing. A system can transition between the EC_HiPerf mode, ECC_HiPerf mode, and ECC_Scrub mode dynamically, thereby attaining the desired benefits of each mode as needed. Enable ECC_Scrub mode where error checking, data correction, and memory scrubbing are enabled. Memory scrubbing corrects a detected single-bit error in the DDR memory. When a single-bit error is detected, additional cycle overhead is associated with correcting the single-bit error in memory. ECC with scrubbing (ECC_Scrub) mode is the ECC mode of highest reliability. In ECC_Scrub mode, ECC is written into memory during writes (partial writes result in a RMW sequence), and corrected data is provided to the PCI/APCI/GART on reads. The AMD-762 system controller checks the ECC returned from memory and sets DDR SDRAM Interface Chapter 3 182 Preliminary Information 24462D--March 2002 AMD-762TM System Controller Software/BIOS Design Guide the ECC status indicators. In addition, the controller also corrects any single-bit errors in memory. ECC_Status The Error Correcting Code Status bits indicate the status of the ECC detect logic as follows: 00 = No error X1 = MED: Multi-bit error detect 1X = SED: Single-bit error detect The ECC status bits and corresponding failing chip-select indicators (see bits below) are set by the first error detected of each type (SED or MED). The AMD-762 system controller does not log any new errors of each type or assert SERR# until software clears the associated ECC_Status bit by writing a 1. ECC_CS_MED The Multiple Bit Error Chip Select status provides the binary encoded chip select for the first multiple-bit error detected by the AMD-762 system controller. The Failing ECC Chip Select is a binary encoded field and is valid only when the ECC_Status bits indicate a multi-bit error was detected. The Single-Bit Error Chip Select status provides the binary encoded chip select for the first single-bit error detected by the AMD-762 system controller. The Failing ECC Chip Select is a binary encoded field and is valid only when the ECC_Status bits indicate a single-bit error was detected. ECC_CS_SED 3.8 Programmable Delay Lines (PDL) This section describes the method used to create the delays necessary for proper DQS operation on the AMD-762 system controller DDR interface. The configuration registers used to control the delays are located in Device 0:Function 1. Note that for most systems, the BIOS should simply set the values recommended in Section 7 on page 219. The following sections provide a detailed description of the PDL operation and the options for BIOS configuration. For memory reads, the DDR devices drive the DQS pins edgealigned with the data, and the AMD-762 system controller must "adjust" the incoming DQS to capture the data. The adjusting of the incoming DQS requires delaying the DQS accordingly for each byte or nibble. Because this timing is very tight, the Chapter 3 DDR SDRAM Interface 183 Preliminary Information AMD-762TM System Controller Software/BIOS Design Guide 24462D--March 2002 AMD-762 system controller implements a Programmable Delay Line (PDL) to adjust the incoming DQS. Each PDL is composed of a selectable buffer chain that is used to delay the incoming DQS strobe for placing the DQS within the valid data window. A separate PDL is implemented for each DQS pin (nine total in non-x4Mode) with additional PDLs (for a total of 18 in x4Mode) placed on the input of the data mask (DM) pins for use when accessing a x4 DIMM. The PDL is only used for read data capture. Because the propagation delay of an individual buffer of the PDL is a function of process, voltage a n d t e m p e ra t u re ( P V T ) , a m e ch a n i s m i s re q u i re d t o compensate for these three variables. This calibration mechanism determines the appropriate delay to apply across PVT. A calibration mechanism is placed near every two PDLs to accurately sense PVT near the actual PDLs used to delay the incoming DQS strobes. Each calibration mechanism is hand placed within the AMD-762 system controller to match gate for gate the actual PDL. This approach minimizes error between the calibration mechanism and the actual PDLs. The range of each PDL is from 1 ns to 2.5 ns (worst case). The resolution of the PDL is equal to one buffer delay inside the AMD-762 system controller. That is, the value in the PDL register that controls the "tap" point of the PDL delay chain represents the number of internal buffer propagation delays. Because the propagation delay of an internal buffer can vary over PVT, the number of buffers (and therefore the value in the PDL control register) can be different at different times (and different across the same AMD-762 system controller device or even different across selected AMD-762 system controller devices), but it can still represent the same delay value in time units. Board effects (signal skews, cross talk, etc.) are incorporated in the timing budget analysis, and they combine to reduce the effective data-valid window width presented to the AMD-762 system controller. The PDL hardware assumes that the effects are symmetric--that is, they shrink the setup and hold times equally. If this symmetry is not the case for the system, then the AMD-762 system controller allows the BIOS to compensate for these effects. The internally delayed DQS (output of the PDL) is used inside the AMD-762 system controller to capture the corresponding 184 DDR SDRAM Interface Chapter 3 Preliminary Information 24462D--March 2002 AMD-762TM System Controller Software/BIOS Design Guide data byte (for x8 and x16 devices) or data nibble (for x4 devices) on a read cycle. The time value of the amount of delay to be applied to each DQS is fixed and is only dependent on the frequency of the system clock. Therefore, the DQS delay required is known a priori and is listed in Table 30. What is not known is how many internal buffer delays equal this required time value over PVT, which is the purpose of the PDL calibration mechanism. Table 30. Default DQS Delay versus System Clock Frequency DQS Delay (ns) 2.0500 ns 1.5625 ns DQS Delay (% of CCLK2X Period) 41.0% 41.7% System Clock Frequency 100 MHz 133 MHz Because the propagation delay of an individual buffer internal to the AMD-762 system controller is a function of PVT, a mechanism is required to compensate for these three variables. As previously mentioned, the delay value is known, but the number of buffers that provides this delay value is not known for a given PVT point. The calibration mechanism provides this piece of information. The mechanism used is a simple measurement of how many buffer delays are required to equal the system clock period. Because the system clock is generated by a PLL in the AMD-762 system controller, and it is already compensated for PVT, the system clock period is independent of PVT. Therefore, the clock period can be assumed to be a constant and can be used to correlate the PDL values (Cal_Dly and Act_Dly) to units of time. Each calibration mechanism inside the AMD-762 system controller measures the 2X SYSCLK period in buffer delays. This measurement can take a few hundred clock cycles, therefore it is done off-line. The calibration mechanism computes a Cal_Dly value that is then transferred into the PDL control register (Act_Dly) at a time when the DQS pins are not active as inputs. The calibration is automatically performed once after reset and once after self-refresh exit, and the resultant value is transferred to each PDL. Re-calibration can be initiated via software. The AMD-762 system controller also has a mode that enables periodic auto calibration. Chapter 3 DDR SDRAM Interface 185 Preliminary Information AMD-762TM System Controller Software/BIOS Design Guide 24462D--March 2002 Periodic auto-calibration mode re-computes the Cal_Dly values and transfers this value into the PDLs. All nine (or 18) calibration mechanisms are enabled/disabled together for autocalibration. This mode is useful in adjusting the delay values during operation. In effect, auto-calibration can adjust for voltage and temperature (VT) drifts during operation. Note that the AMD-762 system controller also allows re-calibration to occur completely under software control when this (autocalibration) mode is disabled. The auto-calibration period is configurable, and the possible periods are 10000, 1000000, 10000000 clock cycles (at 100 MHz, these periods are equal to 100 s, 10 ms, and 100 ms, while at 133 MHz it is somewhat faster). The setting of the autocalibration period should be based on the actual characteristics of the system. Software can control when calibration is done (except for the first computation at reset or an exit from self-refresh). It can either configure the AMD-762 system controller for autocalibration (via the Auto_Cal_En bit), or it can initiate a single recomputation (via the SW_ReCal bit). If software initiates a single recomputation (via the SW_Recal bit), it should also poll for this computation to be done. Because auto-calibration registers are not initialized at reset, it is the responsibility of the BIOS to initialize the SW_Cal_Dly. The SW_Cal_Dly value that BIOS provides is based on a value provided after AMD-762 silicon characterization. The hardware computes the Cal_Dly value that is applied to the PDL based on the SW_Cal_Dly programmed. The SW_Cal_Dly bits are used by AMD-762 system controller to update the delay times in both auto-calibration mode as well as software-initiated calibrations. For example, if the delay required is 1.7 ns and the system clock frequency is 133 MHz, the following is the derivation of the SW_Cal_Dly value: The half-period of system clock = 3.75 ns. 1.7 ns = 45.33% of the half-period. The SW_Cal_Dly value is 0.4533 x 256 = 116 (rounded to nearest integer) = 0x74. The AMD-762 system controller allows software to optionally write to the Act_Dly bits that control each PDL. The value written to the Act_Dly bits is the number of buffer delays 186 DDR SDRAM Interface Chapter 3 Preliminary Information 24462D--March 2002 AMD-762TM System Controller Software/BIOS Design Guide required (rather than a percentage of the clock period). To determine the number of buffer delays, software must first read the Clk_Dly bits and scale this value for the required Act_Dly. For example, if Clk_Dly is 75 buffer delays at 100 MHz, and the BIOS desires a delay of 2.1 ns, the following is the derivation of the Act_Dly value: 75 buffer delays = half-period of system clock = 5 ns 2.1 ns = 2.1 / 5 x 75 = 31.5 buffer delays The Act_Dly value is either 31 or 32 (depending on rounding desired) = 0x1F or 0x20. The AMD-762 system controller provides a configuration bit (Act_Dly_Inh) that inhibits the auto calibration state machine from updating the Act_Dly values after the computation of Clk_Dly and Cal_Dly is completed. If this mode is used, the PDLs (Act_Dly values) are not updated with new Cal_Dly values (whether auto-calibration is enabled or whether software initiates a re-calibration). However, the PDLs are always updated at reset. Upon exit from self-refresh, the Act_Dly_Inh bit determines whether the PDLs are updated or not. This feature can be useful for diagnostic purposes. SW_Recal The Software Re-calibration bit (Dev 0:F1:0x40, bit [7]) provides a way for software to force a re-calibration cycle. This action is allowed only when the auto calibration feature is disabled. A re-calibration is forced when this bit is written to a 1b. This bit also provides status by being cleared when the calibration has completed. BIOS may find it useful to be aware of the completion of the calibration, although from a functional perspective, the DDR memory controller does not require it. When the re-calibration is complete, the hardware recomputes the Cal_Dly values for all PDLs, based on the values of their SW_Cal_Dly fields. The Use Actual Delay bit (Dev 0:F1:0x40, bit [6]) provides a way for software to change the PDL setting manually, which is done by updating the Act_Dly field directly. BIOS should set this bit to indicate to the hardware that it has written to the Act_Dly fields and wants to update the PDLs (all 18) with the newly written Act_Dly values. This method should be used only w hen SW_ R ec a l and Aut o_ Ca l_En bits are not set. If Auto_Cal_En is set, writes to this bit are ignored. Use_Act_Dly Chapter 3 DDR SDRAM Interface 187 Preliminary Information AMD-762TM System Controller Software/BIOS Design Guide 24462D--March 2002 Auto_Cal_En The Auto Calibration Enable bit (Dev 0:F1:0x40, bit [5]) provides a way for BIOS to enable the PDL auto calibration function. When this bit is set, all of the Cal_Dly values are recomputed periodically (according to the setting of the Auto_Cal_Period field) for all PDLs, based on the values of their SW_Cal_Dly fields. If the Act_Dly_Inh bit is not set, the Cal_Dly values are also applied to the Act_Dly. Note: Once Auto_Cal_En is set to 1, clearing it makes the bit a 0, but the auto-calibration logic may perform one more update, depending on when the Auto_Cal_En bit is cleared. Therefore, BIOS should at least wait for the amount of time specified by the Auto_Cal_Period field after clearing the Auto_Cal_En bit before attempting to change any of the PDL parameters. Note: This bit should not be set if the system clock frequency is 66 MHz. Act_Dly_Inh The Actual Delay Update Inhibit bit (Dev 0:F1:0x40, bit [4]) provides a way for BIOS to inhibit an auto-calibration value from updating the PDLs. The setting of this bit affects both auto-calibration and software-initiated calibration but not the Use_Act_Dly method. After an exit from self-refresh, the setting of this bit determines whether the Act_Dly value is updated or not. Note: The internal logic tests this bit just prior to updating the Act_Dly, so the other bits in this register should be taken into consideration when writing to this bit. Auto_Cal_Period The Auto-Calibration Period (Dev 0:F1:0x40, bits [1:0]) bits specify how often an auto-calibration occurs. The autocalibration periods are as follows: 00 = 10000 system clocks 01 = 1000000 system clocks 10 = 10000000 system clocks 11 = Reserved B I O S s h o u l d c o n f i g u re t h i s f i e l d b e fo re s e t t i n g t h e Auto_Cal_En bit. This field should not be altered while Auto_Cal_En is set. Clk_Dly The auto-calibrator's Clock Delay (Dev 0:F1:0x44, bit [31:24] through Dev 0:F1:0x88, bits [31:24]) is read-only and provides DDR SDRAM Interface Chapter 3 188 Preliminary Information 24462D--March 2002 AMD-762TM System Controller Software/BIOS Design Guide the number of PDL buffer delays required to make up a 2X SYSCLK period. This value is used to calculate the actual PDL value. The value returned from this field divided by the clock frequency is the average delay per tap of the PDL. SW_Cal_Dly The auto-calibrator's Software Calibration Delay (Dev 0:F1:0x44, bits [23:16] through Dev 0:F1:0x88, bits [23:16]) provides BIOS access to the overall percentage of the buffers required, based on the total number of buffer delays shown in the Clk_Dly field. This value is used to calculate the actual PDL value. This value should be: 69h at 100 MHz (2.0500 ns 41.0%) 6Bh at 133 MHz (1.5625 ns 41.7%) Cal_Dly The auto-calibrator's Calculated Delay (Dev 0:F1:0x44, bits [15:8] through Dev 0:F1:0x88, bits [15:8]) is read-only and provides the calculated delay based on the auto-calibrator's finding of Clk_Dly and the BIOS-specified SW_Cal_Dly. This value is the final calibration value that is used for the PDL if the Act_Dly_Inh bit (Dev 0:F1:0x40, bit [4]) is not set. If the Act_Dly_Inh bit is set, this calculated value is not used to update the PDLs. The auto-calibrator's Actual Delay (Dev 0:F1:0x44, bits [7:0] through Dev 0:F1:0x88, bits [7:0]) directly specifies the number of PDL taps. BIOS can manually update the PDL by writing a PDL tap value into this register and writing a 1b to the Use Actual Delay bit (Dev 0:F1:0x40, bit [6]). This action should only be done when the auto-calibration logic is disabled by writing a 0b to (Dev 0:F1:0x40, bit [5]). Manually updating the PDL while the auto-calibration logic is enabled could result in unpredictable system operation. Act_Dly 3.8.1 Manual PDL Window Detection The recommended value specified in the SW_Cal_Dly field (Dev 0:F1:0x44, bits [23:16] through Dev 0:F1:0x88, bits [23:16]) is based on calculated round trip timing assuming worst case AMD-762 system controller conditions, worst case DDR DIMM device conditions, and board routing. The most critical timing relationship during a DDR DIMM read is the round trip data delays and the DQS/data relationship relative to each other. Many factors affect the DQS/data relationship. Because of these factors, BIOS itself can determine a precise Chapter 3 DDR SDRAM Interface 189 Preliminary Information AMD-762TM System Controller Software/BIOS Design Guide 24462D--March 2002 SW_Cal_Dly value by performing a manual window detection rather than using the specified values. Manual window detection can be accomplished with the following steps: Disable the PDL auto-calibration feature by setting Dev 0:F1:0x40, bit [5] = 1b0. Disabling auto-calibration prevents auto-calibration interference while BIOS manipulates this process manually. Determine the operating range of each PDL by adjusting each PDL tap from minimum to maximum to determine the data window range. This determination is accomplished by multiple iterative writes to alter the PDL and reading back "expect" data from DDR memory after each PDL tap is altered. For x8/x16 devices, this process is performed at the byte resolution. For x4 devices, this process is performed at the nibble resolution. The Actual Delay is adjusted via Dev 0:F1:0x44, bits [7:0] through Dev 0:F1:0x88, bits [7:0]. After the Actual Delay is configured, BIOS must write a 1b to the Use Actual Delay bit (Dev 0:F1:0x40, bit [6]) to apply the new Actual Delay value. Once the operational range for each byte (for x8/x16 devices) or for each nibble (for x4 devices) is determined, the center point for this window can be determined by dividing these ranges by two, which yields the "target window PDL tap." The average PDL tap value must be determined for knowledge of the expected delay per tap of the PDL. This value can be retrieved by performing a software-initiated calibration. First set the Actual Delay Update Inhibit Dev 0:F1:0x40, bit [4] to a 1b to prevent a calibration update. Initiate a calibration by writing a 1b to Dev 0:F1:0x40, bit [7], and then polling this bit to become a 0b to determine when the calibration is complete. The total number of PDL taps that make up 5 ns (for 100-MHz operation) or 3.75 ns (for 133-MHz operation) can be found in the Clock Delay field for each calibrator in Dev 0:F1:0x44, bits [31:24], through Dev 0:F1:0x88, bits [31:24]. By dividing the appropriate period (as applies to the frequency of the AMD-762TM system controller) by the values found in the Clock Delay fields yields the "average delay per PDL tap." Once the appropriate PDL value is determined for each byte or nibble (as it applies), this value must be converted DDR SDRAM Interface Chapter 3 190 Preliminary Information 24462D--March 2002 AMD-762TM System Controller Software/BIOS Design Guide into a Software Calibration Delay value for the autocalibration logic. This value can be calculated by multiplying the "target window PDL tap" (found above) by the "average delay per PDL tap," which yields the "required PDL tap delay" as a function of time (ns). The Software Calibration delay is specified as a percentage. Therefore, the Software Calibration delay = ((operating period/2) / required PDL tap delay) x 256). The value determined in this calculation must be applied to the Software Calibration Delay field Dev 0:F1:0x44, bits [23:16], through Dev 0:F1:0x88, bits [23:16]. Clear the Actual Delay Update Inhibit Dev 0:F1:0x40, bit [4] to allow calibration updates and then enable the autocalibration system by writing a 1b to Dev 0:F1:0x40, bit [5]. 3.9 DDR I/O Drive Strength The DDR I/O pads are SSTL-2 compatible. The DDR pads have configurable slew rate and drive strength control of N and P transistors, separately. It is the responsibility of BIOS to initialize the pad drive strength and slew rate before any memory accesses. The DDR I/O drive strength and slew controls exist at (Dev 0:F1:0x8C) through (Dev 0:F1:0x9B). Drive strength and slew control are provided for both the P and N transistors to allow for a fine adjustment for proper DDR SSTL-2 crossover points and rise/fall edge rates. Separate drive strength and slew control is provided for the following: Data strobes (DQS) Note: If any chip select is configured to support a x4 DIMM, the DM buses inherit the drive strength and slew setting specified for the data strobes (DQS). Otherwise, the DM pins inherit the drive strength specified for the MDAT pins. This inheritance occurs because a x4 DIMM access uses the DM signals as data strobes (DQS) signals. Data bus (MDAT), ECC bus (MECC), and data mask bus (DM) (See preceding note.) Device clock output (CLKOUTH/L) Note: The AMD-762 system controller provides differential clocks, Chapter 3 DDR SDRAM Interface 191 Preliminary Information AMD-762TM System Controller Software/BIOS Design Guide 24462D--March 2002 CLKOUTH and CLKOUTL, for the DDR DIMMs. This single CLKOUT drive strength and slew setting applies for both polarities of CLKOUT. Device Chip Select (CS[7:0]#) Command bus A (RASA#, CASA#, WEA#, and CKEA#) Command bus B (RASB#, CASB#, WEB#, and CKEB#) Memory address bus A (MAA[14:0]) Memory address bus B (MAB[14:0]) Signal integrity studies have shown that P and N slew settings of 101b and a P drive strength setting of 11b and an N drive strength setting of 10b for all of the signal groups specified above provide adequate edge rates across various registered DIMM devices and population. A proper drive strength and slew setting for (Dev 0:F1:0x8C, bits [31:0]) is 0E_2D_0E_2Dh. 192 DDR SDRAM Interface Chapter 3 Preliminary Information 24462D--March 2002 AMD-762TM System Controller Software/BIOS Design Guide 4 Power Management This cha pte r provides the BIO S requirements for the AMD-762TM system controller's various power management states. The AMD-762 system controller includes logic specifically for the support of the following Advanced Configuration and Power Interface (ACPI) states: S1 Power-On Suspend S3 Suspend to RAM This chapter discusses the BIOS requirements for the AMD-762 sy ste m contro lle r only, an d does not i nclude special requirements for the processor, Southbridge, or the operating system support of each power management state. Note: To accommodate the S3 state, some of the AMD-762 system controller register bits are not initialized to a known value at power-on with the RESET# signal. The BIOS must initialize all of these bits for proper operation, especially when enabling power management features as described in this section. BIOS must also perform a save and restore of all relevant configuration bits in the processor and chipset to support the Suspend to RAM feature. Table 31 on page 194 summarizes the various features required by the AMD-762 system controller to support the different power management states. Note: ACPI C3 state is not supported by the AMD-762 system controller, and the BIOS must not declare C3 support to the operating system through the Fixed ACPI Description Table. The BIOS should declare the following values: * * * A value of 0 in the PM2_CNT_BLK field in the Fixed ACPI Description Table (FADT) A value of 0 in the PM2_CNT_LEN field of the FADT A value of 0 in the X_PM2_CNT_BLK field of the FADT if this ACPI 2.0 extension is supported by the operating system. Chapter 4 Power Management 193 Preliminary Information AMD-762TM System Controller Software/BIOS Design Guide 24462D--March 2002 Table 31. AMD-762TM System Controller Power Management Features for ACPI Support ACPI State C1 C2 S1 S3 X X AMD-762TM System Controller Power Management Feature Disconnect processor when Stop Grant special cycle is detected on AMD AthlonTM processor system bus. Enabled by BIU Status/Control (Dev 0:F0:0x60, bit 17 for CPU 0), (Dev 0:F0:0x60, bit 17 for CPU 1) Memory controller forces DRAM to self-refresh mode Enabled by BIU Status/Control (Dev 0:F0:0x60, bit 17 for CPU 0), (Dev 0:F0:0x60, bit 17 for CPU 1) and Mode/Status Register (Dev 0:F0:0x70, bit 18) DCSTOP# assertion by Southbridge causes AMD-762 system controller to gate off clock trees and DRAM clocks for lower power Enabled when the Stp_Grant_Discon_En bit is set in the BIU Status/Control Register (Dev 0:F0:0x60, bit 17 for CPU 0), (Dev 0:F0:0x60, bit 17 for CPU 1). RESET# assertion in S3 state causes AMD-762 system controller to gate off I/O rings so power can be removed from AGP, PCI, and processor interfaces while VDD_CORE and DDR interface remains powered. Enabled when the Stp_Grant_Discon_En bit is set in the BIU Status/Control Register (Dev 0:F0:0x60, bit 17 for CPU 0), (Dev 0:F0:0x60, bit 17 for CPU 1). X X X X X Each of the various power management features may be optionally enabled with specific configuration bits in the AMD-762 system controller's host bridge configuration space as described in the following sections. 4.1 STPCLK# and Stop Grant The processors enter the Stop Grant state and issue a Stop Grant special cycle on the AMD Athlon processor system busses in response to the assertion of the STPCLK# input signal by the Southbridge. The AMD-762 system controller supports two options for the Stop Grant state: 1. Wait for a Stop Grant Special Cycle from both installed processors and forward the Stop Grant special cycle to the PCI bus, but otherwise continue normal operation (no significant processor power savings). 194 Power Management Chapter 4 Preliminary Information 24462D--March 2002 AMD-762TM System Controller Software/BIOS Design Guide 2. Wait for a Stop Grant Special cycle from both installed processors, disconnect the processor, enter self-refresh, and then forward the Stop Grant special cycle to the PCI bus. This power management state provides a lower power clock controlled state that allows snooping of the processor cache. If the AMD Athlon processor system bus is disconnected, the processor enters a very low-power state. The first option requires no special setup in the AMD-762 system controller other than to write a 0 to the Stp_Grant_Discon_En bit in the BIU Status/Control register (Dev 0:F0:0x60, bit 17 for CPU 0 and Dev 0:F0:0x68, bit 17 for CPU 1). This action causes the AMD-762 system controller to react to the Stop Grant special cycle on the AMD Athlon processor system bus simply by forwarding the cycle to the PCI bus, but not attempting any processor disconnect. No significant power savings occur in this mode. When this option is selected, the BIOS should not declare support for the C2 state in the Fixed ACPI Description Table. The second option requires that the following AMD-762 system controller configuration bits be initialized: The Stp_Grant_Discon_En must be set in the BIU Status/Control registers. When this bit is set, the AMD-762 system controller flushes internal queues after receiving the Stop Grant special cycle, force the DDR DRAM into selfrefresh mode, and forward the Stop Grant special cycle to the PCI bus to the Southbridge. DRAM refresh must be enabled by writing a 0 to the Ref_Dis test bit in the DRAM Mode/Status register (Dev 0:F0:0x58, bit 19). Self-refresh must be enabled by writing a 1 to the Self_Ref_En bit in the Status/Control register (Dev 0:F0:0x70, bit 18). DMA cycles initiated from the PCI bus or AGP interface's PCI bus can be probed in this state. When a cacheable access is initiated on these interfaces, the AMD-762 system controller initiates a connect sequence on the AMD Athlon system bus via the PROCRDY/CONNECT protocol. This mode requires specific configuration registers in the Southbridge to be initialized for proper generation of the STPCLK# signal and resume events. Chapter 4 Power Management 195 Preliminary Information AMD-762TM System Controller Software/BIOS Design Guide 24462D--March 2002 4.2 S1 Power-On Suspend State Requirements The ACPI S1 state uses the Southbridge DCSTOP# signal to gate off the AMD-762 system controller's internal clock trees for a very low-power state. All voltages remain powered on in this mode. To the AMD-762 system controller, the configuration register initialization required for S1 support is the same as that required for Stop Grant support as described in Section 4.1 on page 194. The AMD-762 system controller requires the following BIOS/drivers for S1 support: The Stp_Grant_Discon_En must be set in the BIU Status/Control registers. When this bit is set, the AMD-762 system controller flushes internal queues after receiving the Stop Grant special cycle, forces the DDR DRAM into self-refresh mode, and forwards the Stop Grant special cycle to the PCI bus to the Southbridge. DRAM refresh must be enabled by writing a 0 to the Ref_Dis test bit in the DRAM Mode/Status register (Dev 0:F0:0x58, bit 19). Self-refresh must be enabled by writing a 1 to the Self_Ref_En bit in the Status/Control register (Dev 0:F0:0x70, bit 18). To ensure that no probes are generated, all PCI/AGP traffic must be prevented by the peripheral software drivers before entering the S1 state when DCSTOP# is asserted. It is expected that the drivers have already placed each PCI/AGP peripheral into the D3 state prior to STPCLK# assertion by the Southbridge. While in the S1 state the DRAM clocks (CLKOUT[5:0], CLKOUT[5:0]#) continue to be driven active. This action is required because the registered DIMMs do not support removal of the clock input unless in reset. The S1 sleep state has a very low resume latency because the PLLs are already running. The AMD-762 system controller simply enables its clock trees and reconnects the processor. Because no power is removed from the system, and the RESET# signal is not asserted, all A MD-76 2 s yst em contro lle r 196 Power Management Chapter 4 Preliminary Information 24462D--March 2002 AMD-762TM System Controller Software/BIOS Design Guide configuration registers retain their original value prior to entering the S1 state. The S1 sleep state requires specific configuration registers in the AMD-768 peripheral bus controller or AMD-766 peripheral bus controller to be initialized for proper generation of the STPCLK# and DCSTOP# signals and resume events. 4.3 S3 Suspend to RAM State Requirements The ACPI S3 state achieves maximum power savings and lowlatency resume by shutting off most system power supplies while retaining system context in DRAM. This action requires that the AMD-762 system controller core voltage remain powered on along with the DRAM and part of the Southbridge, while the remaining platform components are powered off. For any system enabling the S3 state, a number of core logic PCI configuration registers and processor MSRs must be saved or restored prior to suspending or restoring S3. Also, certain hidden bits must be unmasked. These requirements apply to all platforms regardless of segment and whether or not AMD PowerNow!TM is used. To the AMD-762 system controller, the configuration register initialization required for S3 support is the same as that required for S1 support. The AMD-762 system controller requires the following of the BIOS/drivers for S3 support: The Stp_Grant_Discon_En must be set in the BIU Status/Control registers. When this bit is set, the AMD-762 system controller flushes internal queues after receiving the Stop Grant special cycle, force the DDR DRAM into selfrefresh mode, and forward the Stop Grant special cycle to the PCI bus to the Southbridge. DRAM refresh must be enabled by writing a 0 to the Ref_Dis test bit in the DRAM Mode/Status register (Dev 0:F0:0x58, bit 19). Self-refresh must be enabled by writing a 1 to the Self_Ref_En bit in the Status/Control register (Dev 0:F0:0x70, bit 18). To ensure that no probes are generated, all PCI/AGP traffic must be prevented by the peripheral software drivers before Power Management 197 Chapter 4 Preliminary Information AMD-762TM System Controller Software/BIOS Design Guide 24462D--March 2002 entering the S3 state when DCSTOP# is asserted. It is expected that the drivers have already placed each PCI/AGP peripheral into the D3 state prior to STPCLK# assertion by the Southbridge. The Suspend to RAM control bits (STR_Control[1:0]) in the DRAM Mode/Status register (Dev 0:F0:0x58) must be properly controlled by BIOS to force the AMD-762 system controller to properly enter and exit the S3 state. Refer to Section 4.3.1 on page 198 for details. To accommodate S3 support, the AMD-762 system controller does not initialize most of the memory controller configuration registers to a known value when RESET# is asserted. It is important that these registers be properly initialized by BIOS during the power-up configuration. Once initialized, the AMD-762 system controller retains these values when resuming from the S3 state. 4.3.1 STR Bit Control for S3 Support Th e S T R _C o n t ro l b i t s a re p rov i d e d t o a l l ow B I O S t o communicate state changes to the AMD-762 system controller's power management logic. Proper control of these bits is required to ensure that the correct sequence is followed when the AMD-762 system controller is entering and exiting the Suspend to RAM state. Each of the three STR_Control modes are described below. Power-On Reset (00) The AMD-762 system controller always sets the STR_Control bits to this value when the RESET# pin is asserted--that is, when powering up from the S3, S4, S5, and Mechanical Off states). The AMD-762 system controller memory controller always drives the DRAM CKE pins Low in this state, forcing the DRAMs inactive, and the memory controller configuration registers retain the values they had prior to the RESET# assertion. BIOS should write this value to the STR_Control bits when resuming from the S4 (Suspend to Disk), S5 (Soft Off), or Mechanical Off states. This action forces the AMD-762 memory controller to follow the normal DRAM initialization sequence as follows: Normal Resume (01) Assert CKE pins to enable clocks at the DRAM DIMMs Power Management Chapter 4 198 Preliminary Information 24462D--March 2002 AMD-762TM System Controller Software/BIOS Design Guide Perform required DRAM initialization sequence, including writes to DRAM mode registers, etc. The BIOS should then follow the normal initialization sequence in this mode, including DRAM configuration and memory sizing, etc. After a hard reset, BIOS should set these bits to 01b and bit 25 of this re gis te r (D R AM I n it ) t o a 1 b w it h in t h e sa me configuration write. If this register is not set to a 01b, setting bit 25 of this register has no effect. This pattern is written by BIOS to inform the AMD-762 system controller memory controller that this is a power-on reset rather than a Suspend To RAM wakeup from reset. Resume from S3 (1X) BIOS should write this value to the STR_Control bits when resuming from the S3 (Suspend to RAM) state. This action instructs the AMD-762 system controller memory controller to perform the proper DDR protocol to exit self-refresh but not attempt to re-initialize the DDR DRAM devices--that is, mode register writes, etc.). Note that this bit is ignored by the memory controller after it exits self-refresh, until the bit is cleared by RESET#. Problems are thus avoided when the AMD-762 system controller periodically enters and exits selfrefresh for S1 and clock throttling. As shown in Figure 5 on page 200, when BIOS writes a 1X to the STR_Control field upon exiting the S3 state, the AMD-762 system controller simply takes the DRAM out of self-refresh mode. At this time all of the AMD-762 memory controller configuration registers retain their original values programmed prior to entry to the S3 state, thus allowing BIOS immediate access to memory for the restoration of all other system configuration registers and context restoration. Refer to Section 1.1.3 on page 4 for a list of the AMD-762 system controller configuration registers that are not set to a known value when the RESET# pin is asserted. Chapter 4 Power Management 199 Preliminary Information AMD-762TM System Controller Software/BIOS Design Guide 24462D--March 2002 Resume from S3/S4/S5 or mechanical off states, RESET# asserted, forces 00 00 * DRAM CKE pins are Low, all DRAM CLKOUT pins are enabled STR_Control Resume from S4/S5 or mechanical off states, BIOS writes 01 Resume from S3 state, BIOS writes 1X STR_Control 1X * * Powerdown or enter S3 state, STR_Control bits reset to 00 by assertion of RESET# pin STR_Control 01 DRAM CKE pins are asserted by the AMD-762 system controller. BIOS initiates the AMD-762 system controller to start DRAM. power-up initialization process, including disabling any unused DDR clocks, writing to DRAM mode registers, etc. BIOS continues normal system initialization and POST process. * * AMD-762TM system controller asserts DRAM CKE pins and exits self-refresh mode. The AMD-762 system controller retains the value of all memory controller configuration registers; all other registers are cleared to their power-up values. BIOS disables any unused DDR clocks. BIOS can now begin restoring all other configuration registers from DRAM. * * * Figure 5. Suspend to RAM (STR_Control) Bits Usage 4.4 Clock Throttling Clock throttling is a power management mechanism that periodically causes the assertion of the STPCLK# signal to the processor to achieve lower system power. Clock throttling can be accomplished through a combination of hardware and software and can be performed at regular intervals--that is, modulating the STPCLK# pin or through a more sophisticated system such as implementing thermal sensors on the motherboard. The AMD-762TM system controller supports clock throttling with the same hardware mechanisms that are used for Stop Grant support and requires the following BIOS configuration register initialization. The Stp_Grant_Discon_En must be set in the BIU Status/Control registers. When this bit is set, the AMD-762 system controller flushes internal queues after receiving the Stop Grant special cycle, forces the DDR DRAM into Power Management Chapter 4 200 Preliminary Information 24462D--March 2002 AMD-762TM System Controller Software/BIOS Design Guide self-refresh mode, and forwards the Stop Grant special cycle to the PCI bus to the Southbridge. DRAM refresh must be enabled by writing a 0 to the Ref_Dis test bit in the DRAM Mode/Status register (Dev 0:F0:0x58, bit 19). Self-refresh must be enabled by writing a 1 to the Self_Ref_En bit in the Status/Control register (Dev 0:F0:0x70, bit 18). DMA cycles initiated from the PCI bus or AGP interface PCI bus can be probed while in the Stop Grant state during clock throttling. When a cacheable access is initiated on these interfaces, the AMD-762 system controller initiates a connect sequence on the AMD Athlon system bus via the PROCRDY/CONNECT protocol. Note that when using clock throttling, the Southbridge must be programmed to wait for the Stop Grant special cycle before changing the state of the STPCLK# signal. 4.5 DDR DRAM Clock Enables The AMD-762 system controller is designed to provide BIOS the ability to disable any unused DDR DRAM clock pairs to reduce power and system noise. These clock pairs are controlled by the Clk_Dis[5:0] field in the DRAM Mode/Status register (Dev 0:F0:0x58). The AMD-762 system controller provides enough differential clock pairs to support four registered DIMMs. The usage of these clocks is motherboard-specific (i.e., which clock pairs connect to which DIMM clock inputs). The Clk_Dis bits are initialized to 0 when RESET# is asserted, thus guaranteeing that all DRAM clock pairs are enabled when exiting the S3 state. It is recommended that clock pairs that are connected to unused DIMM slots be disabled by BIOS. Note that because the values programmed by BIOS during power-on initialization are not maintained when entering the S3 state, BIOS is required to write to the Clk_Dis field when restoring the AMD-762 system controller configuration registers. Chapter 4 Power Management 201 Preliminary Information AMD-762TM System Controller Software/BIOS Design Guide 24462D--March 2002 202 Power Management Chapter 4 Preliminary Information 24462D--March 2002 AMD-762TM System Controller Software/BIOS Design Guide 5 PCI Bus Interface This chapter provides additional details of some of the AMD-762TM system controller PCI interface options that affect system performance and compliance to the PCI Local Bus Specification, Revision 2.2, as well as some recommended settings for the AMD-762 system controller configuration register bits. The features and options discussed are as follows: 66-MHz primary bus option PCI delayed transactions and target latency PCI transaction ordering Special arbitration options for Southbridges with legacy DMA requirements Performance enhancement options, including read prefetching and PCI chaining 5.1 66-MHz Primary Bus Option The AMD-762 system controller drives the PCI clocks for systems implementing a 66-MHz primary PCI bus. There are three PCI bus clocks provided for this configuration as follows: PCI_66CLK[0] should be connected to the Southbridge and must be fed back into the Northbridge for clock skew control. PCI_66CLK[2:1] are available for connection to optional slots or peripheral devices on the motherboard. The AMD-762 system controller provides configuration bits t h a t al low t h es e c lo ck s t o b e o p t io n a lly d is ab le d fo r 33-MHz-only system configurations or 66/33 MHz where the optional slots are not required. Note: BIOS must never disable PCI_66CLK[0] in 66/33-MHz configurations! This action will cause the system to lock up because the Southbridge clock will be disabled. The configuration bits are located in the PCI Control Register (Dev 0:F0:0x4C, bits [10:8]). Chapter 5 PCI Bus Interface 203 Preliminary Information AMD-762TM System Controller Software/BIOS Design Guide 24462D--March 2002 5.2 Delayed Transactions and Ordering Rules Usage The AMD-762 system controller provides three transaction operating modes for the PCI bus host bridge interface as listed in Table 32 on page 204. BIOS should program the bits listed in Table 32 to only one of these combinations for best results. Table 32. AMD-762TM Processor System Controller PCI Read Transaction Options Description No PCI transaction ordering or target latency rules are enforced. Delayed transactions are disabled, but masters are not retried by the AMD-762TM system controller during memory reads (unless the PCI_WR_Post_Rty bit is set in the PCI Arbitration Register at Dev 0:F0:0x84). This mode is not fully PCI 2.2-compliant because the AMD-762 system controller host bridge may consume greater than 32 PCI bus clocks during memory read transactions, and transaction ordering is not strictly enforced. Delayed transactions are enabled and target latency rules are enforced. This mode is not fully PCI 2.2-compliant because transaction ordering rules are not strictly enforced. Delayed transactions are enabled, target latency and transaction ordering rules are enforced. This mode provides full PCI 2.2-compliance. PCI_DT_En PCI_OR_En Tgt_Latency Dev 0:F0:0x4C, bit 2 Dev 0:F0:0x4C, bit 1 Dev 0:F0:0x84, bit 23 0 Disabled 0 Disabled 0 Disabled 1 Enabled 1 Enabled 0 Disabled 1 Enabled 1 Enabled 1 Enabled The effects of the settings described in Table 32 above are described further in the following sections. 5.2.1 Delayed Transactions and Target Latency Delayed transactions and read target latency should be enabled and disabled together in the AMD-762 system controller, such that both bits are either set or cleared. Setting the read target latency bit (Tgt_Latency) forces the AMD-762 system controller to disconnect the current PCI memory read cycle in progress when the defined maximum allowable latency has expired. This latency is defined in the PCI Local Bus Specification, Revision 2.2, as 16 PCI clocks (32 PCI clocks for host bridges that must snoop processor caches). When the read target latency is reached, the AMD-762 system controller asserts the STOP# signal, thus disconnecting the PCI master (retry). The master is then PCI Bus Interface Chapter 5 204 Preliminary Information 24462D--March 2002 AMD-762TM System Controller Software/BIOS Design Guide obligated by protocol to retry the same cycle after rearbitration, in anticipation that the read has completed in the memory subsystem, thus the next read cycle falls within the maximum target latency. Setting the delayed transaction enable (PCI_DT_En) causes the AMD-762 system controller to latch the address and read command that was initiated by the external master when the read target latency timer expires, thus allowing the PCI target and memory controller logic to independently complete the read so that the next time the original master retries the read, the data is ready to return immediately (assumes the PCI_WR_Post_Rty bit is not set in the PCI Arbitration Register (Dev 0:F0:0x84, bit 14). There are two reasons delayed transactions may be enabled: 1. For systems that must meet the target latency requirement, delayed transactions are better because the memory read cycle is queued in the AMD-762 system controller memory controller after the PCI master is disconnected and while it is re-arbitrating for the PCI bus. This action provides a higher likelihood that when the master retries the transaction, the read data is immediately available. 2. Delayed transactions free up the PCI bus during the time that the memory subsystem is retrieving the read data, for peer-to-peer PCI traffic between other PCI masters and agents. Unfortunately, this type of traffic is rare in most systems. It should be noted that the AMD-762 system controller supports only a single-level delayed transaction queue, thus the performance benefit may be minimal and may actually be worse with delayed transa ct ions enabled under some conditions. The following sec t io ns provide exa mples of PCI re ad transactions with delayed transactions enabled and disabled. Note that in both examples the read target latency feature enable is set the same as the delayed transaction feature enable. Delayed Transactions and Target Latency Disabled Chapter 5 This example assumes that a memory read transaction is initiated by a PCI master and that the AMD-762 system PCI Bus Interface 205 Preliminary Information AMD-762TM System Controller Software/BIOS Design Guide 24462D--March 2002 controller is unable to return data within the specified 32 PCI clock latency. 1. The AMD-762 system controller initiates a memory read to the memory controller and simultaneously issues a probe to the processor. The memory subsystem is unable to return the data within 32 PCI clocks, so it continues to hold the bus (DEVSEL# active, STOP#, and TRDY# inactive). 2. A second PCI master requests the bus to access main memory, and it receives a bus grant from the AMD-762 system controller PCI arbiter, but it must wait until the memory read cycle initiated by the previous master is completed. If this master's cycle was targeted to another PCI agent, it still could not begin the transaction because the bus is tied up by the previous master and the AMD-762 system controller. 3. Some number of PCI clocks later, the memory subsystem returns read data to the master completing the transaction. The bus goes idle, so the next master begins its transaction. Delayed Transactions and Target Latency Enabled This example assumes that a memory read transaction is initiated by a PCI master and that the AMD-762 system controller is unable to return data within the specified 32 PCI clock latency. 1. The AMD-762 system controller latches the memory read command and the address, and initiates a memory read to the memory controller and simultaneously issues a probe to the processor. The memory subsystem is unable to return the data within 32 PCI clocks, so it asserts the STOP# signal while TRDY# remains inactive. This action causes the master that originated the cycle to disconnect, and it must re-arbitrate for the bus. Meanwhile, the AMD-762 system controller memory controller continues to process the enqueued memory read transaction. 2. A second PCI master's bus request is now granted. * If the request is a read from main memory, the AMD-762 system controller retries the cycle but does not queue the transaction because it already has an outstanding delayed transaction in progress. * If the request is to a peer PCI agent, then the transaction can continue in parallel to the memory cycle being completed by the AMD-762 system controller. 206 PCI Bus Interface Chapter 5 Preliminary Information 24462D--March 2002 AMD-762TM System Controller Software/BIOS Design Guide 3. The original master wins bus arbitration and retries its read command, and the AMD-762 system controller now responds with the read data within the specified maximum target read latency. In summary, if compliance to the target latency rules is desired, then it is recommended that delayed transactions enable and the target latency bits are enabled. 5.2.2 Transaction Ordering Rules The PCI Local Bus Specification, Revision 2.2, defines various transaction ordering rules to accommodate the producerconsumer model and to prevent deadlock conditions on the bus under certain conditions. The AMD-762 system controller provides the ability to optionally disable strict adherence to the transaction ordering rules if desired. The ordering rules are defined such that data and its associated flags are visible by any agent on any segment of the PCI bus. In typical systems, however, this visibility is not necessary, as both data and flags typically reside in main system memory. It may be possible to achieve slightly better PCI bus performance when ordering rules compliance is disabled, because PCI masters attempting to read main memory are not disconnected to force the flushing of posted write FIFOs in the AMD-762 system controller. Fi g u re 6 o n p a g e 2 0 9 i l l u s t ra t e s a n ex a m p l e s y s t e m implementation with data and associated flags stored in different locations. In this example, the flag is stored in main memory (DRAM) and the data is stored in the PCI agent. The sections that follow describe the behavior in a system with and without ordering rules compliance. With Ordering Rules Enabled Using Figure 6 as an example, the following case describes the behavior of the AMD-762 system controller when ordering rules are followed. 1. The processor writes data (memory write) destined to an agent on the PCI bus, and the data is posted in the AMD-762 system controller PCI posting buffer. 2. The processor then sets a flag in memory, informing the PCI agent that the data is written. Chapter 5 PCI Bus Interface 207 Preliminary Information AMD-762TM System Controller Software/BIOS Design Guide 24462D--March 2002 3. The PCI master reads the flag, but this action causes the data previously written by the processor to be flushed from the AMD-762 system controller posted write buffer. The PCI master is disconnected by the AMD-762 system controller (STOP# active with TRDY# inactive) to allow the AMD-762 system controller to write the data to the PCI agent. 4. The PCI master regains bus ownership and attempts to read the flag again. This time it successfully reads the flag and the previously posted write data has already been written to the master's target interface. It should be noted that this configuration is rare, as most systems place the data and the flag in main memory. With Ordering Rules Disabled Using Figure 6 as an example, the following case describes the behavior of the AMD-762 system controller when ordering rules are not followed. 1. The processor writes data (memory write) destined to an agent on the PCI bus, and the data is posted in the AMD-762 system controller PCI posting buffer. 2. The processor then sets a flag in memory, informing the PCI agent that the data is written. 3. The PCI master reads the flag, but the associated data (previously written by the processor) has not been flushed from the AMD-762 system controller posted write buffer. This situation results in a data incoherency. Again, as in the case when ordering rules are enabled, note that this configuration is rare, as most systems place the data and the flag in main memory. The AMD-762 system controller provides the ordering rules feature for compliance to the PCI Local Bus Specification, Revision 2.2. 208 PCI Bus Interface Chapter 5 Preliminary Information 24462D--March 2002 AMD-762TM System Controller Software/BIOS Design Guide CPU Northbridge DRAM Producer DATA FLAG Data Posted in Northbridge PCI Bus PCI Agent * * * Consumer Producer (CPU) writes data to the agent (consumer), data is posted in the bridge posting buffer. Producer sets flag in memory. Consumer reads flag, causing the posting buffer to be automatically flushed with ordering rules compliance enabled. Figure 6. Example of System with Flag and Data Stored across PCI Bus Domain 5.2.3 Special Arbitration Considerations for the Southbridge To accommodate legacy DMA as is supported in the AMD-768TM peripheral bus controller or AMD-766TM peripheral bus controller (the devices connected to the AMD-762 system controller's SBREQ# and SBGNT# pins), the AMD-762 system controller makes special exceptions in the arbitration for the Southbridge. The Southbridge is not preempted or disconnected when it gains access to the PCI bus as a master. This design prevents potential deadlock conditions that can occur with legacy DMA. There are no BIOS requirements to enable or disable this functionality. Before winning bus arbitration, the AMD-762 system controller's internal memory read and write queues can optionally be locked and flushed. This option is controlled by the SB_Lock_Dis bit in the PCI Arbitration Control register (Dev 0:F0:0x84, bit 8). This bit is cleared for normal operation. Chapter 5 PCI Bus Interface 209 Preliminary Information AMD-762TM System Controller Software/BIOS Design Guide 24462D--March 2002 By default, the AMD-762 system controller does not allow the SBREQ# PCI request to be preempted by requests on the normal REQ#[6:0] pins, and it does not disconnect the Southbridge once it has started a transfer. 5.3 PCI Performance Optimization Options In addition to transaction level options as listed in Section 5.2 on page 204, the AMD-762 system controller PCI bus interface provides various system level options that can be used to tune the system performance. Each of these options are described in the following sections. 5.3.1 Read Prefetching When the AMD-762 system controller is the target of PCI memory read accesses to system memory, the AMD-762 system controller's PCI target interface initiates a probe of the AMD AthlonTM processor's cache and a read of eight quadwords (a single cache line) from memory. Setting the read prefetching bit (PCI_Pref_En, Dev 0:F0:0x84, bit 1) causes the AMD-762 system controller to prefetch another eight quadwords from memory, speculating that the PCI master will request another cache line at the next cache-aligned address. The obvious advantage to read prefetching is that masters that are reading multiple contiguous cache lines of data can stream this data more effectively on the PCI bus. The disadvantage is that it could result in wasted bandwidth of the memory subsystem of the prefetched data that is purged because it was not needed by the PCI master. 210 PCI Bus Interface Chapter 5 Preliminary Information 24462D--March 2002 AMD-762TM System Controller Software/BIOS Design Guide 5.3.2 PCI Chaining PCI chaining is a feature designed to optimize memory writes from the processor to the PCI bus. Chaining simply causes write combining at the PCI interface, such that four quadword CPU memory writes to contiguous addresses are chained together, resulting in a single PCI burst-write instead of separate nonburst writes. PCI chaining is enabled by the PCI_Chain_En bit in the PCI A r b i t ra t i o n C o n t r o l re g i s t e r ( D e v 0 : F 0 : 0 x 8 4 ) . I t i s re c o m me n d e d t h a t t h i s b i t a lways b e s e t fo r o p t i m a l performance. 5.3.3 PCI Bus Parking The PCI Local Bus Specification, Revision 2.2, requires that a default bus owner be designated that always drives the bus to a known value to prevent the bus from floating for long idle periods. The AMD-762 system controller provides two options for bus parking: Park on the AMD-762 system controller--that is, CPU accesses to PCI agents Park on the last master that had bus tenure Arbitration latency on an idle bus for the agent that has default ownership (bus is parked on that agent) is zero PCI clocks, whereas it is two PCI clocks for all other masters. PCI bus parking is controlled by the Park_PCI bit in the PCI A r b i t ra t i o n C o n t r o l re g i s t e r ( D e v 0 : F 0 : 0 x 8 4 ) . I t i s recommended that this bit be cleared to 0 to force parking the bus on the AMD-762 system controller. Chapter 5 PCI Bus Interface 211 Preliminary Information AMD-762TM System Controller Software/BIOS Design Guide 24462D--March 2002 212 PCI Bus Interface Chapter 5 Preliminary Information 24462D--March 2002 AMD-762TM System Controller Software/BIOS Design Guide 6 AGP Interface This chapter details some of the specific BIOS requirements for programming the AMD-762TM system controller's AGP interface. 6.1 AGP Dynamic Compensation Requirements To accommodate the high-speed requirements of 4X AGP rates, the AMD-762 system controller provides circuitry designed to automatically compensate for motherboard impedance on the AGP interface over the range of temperature and voltage, by dynamically adjusting the drive strength of the AMD-762 system controller I/O pads when 1.5-V signalling is selected by the AGP card. This action requires proper initialization by BIOS as described in this section. Two separate 32-bit c o n f i g u ra t i o n re g i s t e rs a re u s e d t o c o n t ro l AG P I / O characteristics: 1. AGP Dynamic Compensation register, Dev 0:F0:0xB4 2. AGP Compensation Bypass register, Dev 0:F0:0xB8 Two modes are provided in the AGP compensation circuitry: Automatically compensate once or at regular intervals by adjusting the drive strengths of the AGP interface I/O cells. In this case, BIOS is not required to program the drive strength values. Bypass the compensation and allow BIOS to write drive strength values directly to the I/O cells. The AMD-762 system controller allows the AGP strobe signals (ADSTB[1:0], ADSTB[1:0]#) to be controlled independently from all other AGP signals, including the ability to bypass compensation for one set of signals while the other set is compensated and vice-versa. The slew rate for the AGP interface pins is also programmable by BIOS but is not changed by the autocompensation logic. Chapter 6 AGP Interface 213 Preliminary Information AMD-762TM System Controller Software/BIOS Design Guide 24462D--March 2002 Additional compensation details are provided in the following sections, and specific programming recommendations are listed in Section 6.3 on page 217. 6.1.1 The AGP 4X Dynamic Compensation Register AGP compensation is controlled by the AGP 4X Dynamic Compensation register (Dev 0:F0:0xB4). This register contains additional fields that are not directly related to compensation but control various attributes of the AMD-762 system controller AGP interface. This section provides additional details about the fields related to compensation. PVal, NVal The PVal and NVal are read-only fields that can be used to determine the drive strength values being automatically written to the AGP I/O pads by the compensation logic. These a p p ly o n ly t o t h e s i g n a l s u s e d fo r d a t a t ra n s f e r a n d status/control--that is, not the AGP strobes. Typically the values read back allow BIOS to determine if the correct compensation resistors are installed on the motherboard. These fields are used to enable 1.5-V signalling compensation at regular intervals, which is the suggested method for all 4X AGP non-strobe signals. The Quantum_Cnt field can be programmed for the maximum value (6.4 seconds), because it is not expected that a more frequent adjustment is required. The compensation is scheduled by the AMD-762 system controller such that changing the drive strength values does not interfere with AGP traffic. If compensation bypass is selected for both the data transfer and strobe pins (both the BYPXfer and BYPStrb bits are set in the Compensation Bypass register) then these fields are ignored. Quantum_Cnt, Always_Compensate Do_Compensate, Comp3.3 These bits can be used in two cases: To force a normal, single compensation cycle in 1.5-V signalling mode to update the AGP I/O drive strengths, and to prevent any further updates. In this case, the Do_Compensate bit may be set (Comp3.3 should be cleared), and the AGP interface must not be enabled until this bit is read back as a 0, indicating that the compensation cycle is complete. 214 AGP Interface Chapter 6 Preliminary Information 24462D--March 2002 AMD-762TM System Controller Software/BIOS Design Guide To force a single compensation cycle in 3.3-V signalling mode (typically used for debug only). In this case, both the Do_Compensate and the Comp3.3 bits should be set, and the AGP interface must not be enabled until this bit is read back as a 0, indicating that the compensation cycle is complete. If compensation bypass is selected for both the data transfer and strobe pins (both the BYPXfer and BYPStrb bits are set in the Compensation Bypass register) then these fields are ignored. 6.1.2 Selection of 1.5- or 3.3-V AGP Signalling The selection of the AGP signalling type (1.5 V versus 3.3 V) is done by the AGP card via the TYPEDET# pin when it is installed in the AGP slot. AGP cards operating in 3.3-V signalling mode have their TYPDET# pin unconnected. Cards operating in 1.5-V signalling mode have the pin connected to VSS, forcing it to 0. The AMD-762 system controller latches the value of the TYPEDET# pin at reset, and BIOS can read this value in the Configuration Status register (Dev 0:F0:0x88, bit 25). The allowable rates at each signalling level are shown in Table 33 as listed in the Accelerated Graphics Port Interface Specification, Revision 2.0. Table 33. AGP Rate 1X 2X 4X Allowable AGP Rate versus Signalling Level 1.5-V Signalling Supported Supported Supported 3.3-V Signalling Supported Supported Not Supported S e c t io n 6 . 3 o n p a g e 2 1 7 d e sc r i b e s t h e re c o m m e n d e d initialization sequence for reading this value and configuring various AMD-762 system controller parameters accordingly. Chapter 6 AGP Interface 215 Preliminary Information AMD-762TM System Controller Software/BIOS Design Guide 24462D--March 2002 6.2 Feature Override Bits for AGP Cards The AMD-762 system controller supports 1X, 2X, and 4X AGP rates as well as fast writes. The capability to support these features is normally reported to the operating system via the AGP Status register (Dev 0:F0:0xA4) as defined by the Accelerated Graphics Port Interface Specification, Revision 2.0. The operating system is thus able to determine and select the highest rate supported by both the AGP card and the AMD-762 system controller. The AGP interface of the AMD-762 system controller includes two configuration bits that can be used to override the AGP Status register and to prevent reporting 4X and fast write capability. These bits are required to allow operation with AGP cards that operate with 3.3-V signalling, but still report 4X capability to the operating system. The problem thus created is because the operating system attempts to place the card and the AMD-762 system controller into 4X mode, but this speed is not supported when 3.3-V signalling is selected. The solution is for the AMD-762 system controller to report capability of a maximum of 2X AGP speed in this configuration. The two override bits are described below, and specific programming recommendations are listed in Section 6.3. 4X_Override This bit is used to force the 4X rate bit to 0 in the AGP Status register (Dev 0:F0:0xA4, bit 2). After reset, the rate field in the AGP Status register is set to all 1s, indicating support for a maximum of 4X AGP speed. Setting the 4X_Override bit automatically forces this field to 011, indicating a maximum of 2X support. This override mechanism is required because the AGP Status register is defined as a read-only register in the AGP specification. This bit indirectly enables fast write support in the AMD-762 system controller. Fast write support is reported to the operating system through the AGP Status register as described above for the rate field, but the FW status bit in the AGP Status register defaults to 0 (not supported) in the AMD-762 system controller. The FW_Enable bit should be set if this feature is desired. Section 6.3 provides guidelines for setting these bits. FW_Enable 216 AGP Interface Chapter 6 Preliminary Information 24462D--March 2002 AMD-762TM System Controller Software/BIOS Design Guide 6.3 BIOS Initialization Requirements This section lists the steps in an algorithm recommended to properly configure the AMD-762 system controller AGP fast write and rate features, as well as the compensation and slew rate values. This BIOS algorithm must properly detect the AGP card's signalling type (1.5 V or 3.3 V) and enable the appropriate features as listed in the steps below. Note that these steps are require before the AGP interface is enabled. 1. Detect the signalling level (1.5 V or 3.3 V) by reading the value of the TYPEDET# pin that was latched by the AMD-762 system controller at reset. This value can be read in the Configuration Status register, Dev 0:F0:0x88, bit 25. * If 0, then 1.5-V signalling is selected by the AGP card. If 1, then 3.3-V signalling is used. 2. Configure the override bits according to the signalling level as listed in Table 34 on page 218 and the following notes. * If 1.5 V, then the 4X_Override bit should be cleared, and the FW_Enable bit should be set in the AGP 4X Dynamic Compensation register (Dev 0:F0:0xB4, bits 6 and 7, respectively). This action causes the AGP Status register (Dev 0:F0:0xA4) to report 4X and fast write capability to the operating system. * If 3.3 V, then the 4X_Override bit should be set, and the FW_Enable bit should be cleared in the AGP 4X Dynamic Compensation register (Dev 0:F0:0xB4, bits 6 and 7, respectively). This action causes the AGP Status register (Dev 0:F0:0xA4) to report a maximum rate of 2X, and no fast write capability to the operating system. 3. Program the appropriate compensation, drive strength, bypass, and slew rates to the AGP I/O pads in the AGP 4X Dynamic Compensation and AGP Compensation Bypass register according to Table 34 below. Chapter 6 AGP Interface 217 Preliminary Information AMD-762TM System Controller Software/BIOS Design Guide 24462D--March 2002 Table 34. AGP I/O Settings for 1.5- and 3.3-V Signalling Bit/Field Name FW_Enable 4X_Override Comp3.3 PCI Always_Compensate Do_Compensate BYP_PDrvXfer BYP_NDrvXfer BYPXfer PSlewXfer NSlewXfer BYP_PDrvStrb BYP_NDrvStrb BYPStrb PSlewStrb NSlewStrb Bits [7] [6] [5] [2] [1] [0] [31:28] [27:24] [23] [19:18] [17:16] [15:12] [11:8] [7] [3:2] [1:0] 1.5-V Value TYPEDET# = 0 1 0 0 0 1 0 Don't Care Don't Care 0 11 11 1111 1111 1 11 11 3.3-V Value TYPEDET# = 1 0 1 0 0 0 0 Don't Care Don't Care 0 11 11 Don't Care Don't Care 0 11 11 Register Dev 0:F0:0xB4 Dev 0:F0:0xB8 6.4 AGP Miniport Driver Requirements AMD has found that some early generation 4x AGP cards were not consistently implemented using published 4x AGP guidelines for AGP signal impedance and routing. These AGP cards do not work reliably with the default AGP drive-strengths of the AMD-762 system controller. As a result, AMD has developed a mini-port solution to adjust the AMD-762 system controller AGP drive strengths to the optimal levels for these early generation AGP cards as identified by the vendor and device ID in PCI configuration space. AMD does not plan for any current or future generation AGP cards to experience any incompatibilities with the AMD-762 system controller. If a card is identified that requires a drive strength change, the AMD mini-port or the AGP card is updated to allow compatibility. 218 AGP Interface Chapter 6 Preliminary Information 24462D--March 2002 AMD-762TM System Controller Software/BIOS Design Guide 7 Recommended BIOS Settings This chapter provides the recommended BIOS settings for the initialization of some of the key AMD-762TM system controller configuration registers. Registers that change based on the system implementation, such as memory space and sizing, AGP GART region, DDR DIMM timing, etc., are not included here because they are platform-specific. The following notes apply to the recommended settings tables in this section: All items keyed as BOLD CAPITALS should be set or controlled by BIOS. This is mandatory. No setting can be assumed by default. Refer to the actual configuration register descriptions for details of each bit. These can be found in "AMD-762TM System Controller Programmer's Interface" on page 9 of this document. The final and precise definition of bits in the SPD of a DDR DIMM can be found in JEDEC reference materials and specifications. Values that are shown as x..xh or x..xb must be set by BIOS (unless the Key field shows register as read-only). Numerical Values shown with h or b are preferred settings. For any system enabling the S3 state, a number of core logic PCI configuration registers and processor MSRs must be saved or restored prior to suspending or restoring S3. Also, certain hidden bits must be unmasked. These requirements apply to all platforms regardless of segment and whether or not AMD PowerNow!TM is used. Chapter 7 Recommended BIOS Settings 219 Preliminary Information AMD-762TM System Controller Software/BIOS Design Guide 24462D--March 2002 7.1 PCI Bus 0, Device 0, Function 0 Registers PCI Bus 0, Device 0, contains configuration registers that are mostly specific to the AMD-762 system controller and its processor, DDR SDRAM, AGP, and PCI bus interfaces. The Bus 0, Device 0 space contains two separate functions as follows: Function 0 contains standard PCI configuration space, timing and arbitration control for each interface, and memory decode registers. Function 1 contains DDR drive strength control and calibration control for the programmable delay lines (PDLs) of the DRAM interface. 220 Recommended BIOS Settings Chapter 7 Preliminary Information 24462D--March 2002 AMD-762TM System Controller Software/BIOS Design Guide Registers ----Bits 0x0x0x00h 31:16 15:0 0x0x0x04h 31 30 29 28 27 26:25 24 23 22 21 20 19:10 9 8 7 6 5 4 3 2 1 0 0x0x0x08h 31:24 23:16 15:8 7:0 KEY: Register Bit Name PCI ID Device ID Vendor ID PCI Command and Status PERR SERR Sent Master ABRT Target ABRT Target ABRTS Signaled DEVSEL_Timing Data_PERR FastB2B UDF 66M Cap_Lst Reserved FBACK SERR, System Error Enable Step PERR VGA Palette Snoop MWINV SCYC MSTR MEM IO PCI Rev ID and Class Code Class Code Sub_Class Code Prog. I/F Revision ID Initialized/ Required Value 700Ch 1022h 0b yb yb yb 0b 01b 0b 0b 0b Xb 1b 000h 0b yb 0b 0b 0b 0b 0b 1b 1b 0b 06h 00h 00h 1yh Actual Value Key fcn( ) Notes Dual-processor DDR Northbridge AMD Not supported R/W/1C, from AMD-762TM system controller R/W/1C, from bus master R/W/1C, from bus master target Not supported r r r c u u r r r r r r r r u r r r r r r B r r r r r Based on the value latched on the AD[15] pinstrap. Set for 66 MHz enabled, cleared for 66 MHz disabled. 0 = Disable, 1 = Enable PCI memory access enable IO access disable on PCI bus Bridge device Host/PCI bridge Host/PCI bridge Rev B1 = 11h, B2=12h, B3=13h c = Calculated/set by AMD-762TM sys. controller internal logic F = Performance enhancement set by BIOS E = Elective BIOS function B= Mandatory BIOS function A= AGP setup by BIOS P= Power management setup by BIOS o = Setup by OS or OS driver r = Hardcoded and reserved u = PCI operational user interface Chapter 7 Recommended BIOS Settings 221 Preliminary Information AMD-762TM System Controller Software/BIOS Design Guide 24462D--March 2002 Registers ----Bits 0x0x0x0Ch 31:24 23:16 15:8 7:0 0x0x0x10h 31:25 24:4 3 2:1 0 0x0x0x14h 31:12 11:4 3 2:1 0 0x0x0x18h 31:24 Description PCI Latency Timer and Header Type Reserved Header_Type Lat_Timer Reserved BAR0:AGP Virtual Address Space AGP Base Address Register 0 GART AGP Aperture Address Base Address Low Flags BAR0 mem as Prefetchable BAR0 Type mem as 32 bits Flags BAR0 as MEMORY Address Space BAR1:GART Memory Mapped Register Base GART Memory Mapped Base Address Register Settable portion of Address GART Memory Mapped Base Address Register Low, hardwired to force 4 Kbytes BAR1 mem Prefetchable BAR1 Type mem as 32 bits Flags BAR1 as MEMORY BAR2:PM2_BLK I/O Register Base Reserved PM2_BLK I/O Address register base address Settable portion of address Reserved Flags BAR2 as I/O Address Space Initialized/ Required Value Actual Value Key fcn( ) Notes 00h 00h 20h 00h r r B r xxxx_xxxb 0b00_000h 1b 00b 0b A r r r r Always 0 = 32 Mbytes minimum PCI specification PCI specification PCI specification xxxx_xh 00h 1b 00b 0b A r r r r PCI specification PCI specification PCI specification 00h xx_xxxh xxb 0b 1b r Assigned by PCI enumeration Power Management function. ACPI IO Address space, see PM En/Dis bit @0x0x0x84[7] PCI specification 23:2 P 1 0 KEY: r r B= Mandatory BIOS function A= AGP setup by BIOS P= Power management setup by BIOS o = Setup by OS or OS driver r = Hardcoded and reserved u = PCI operational user interface c = Calculated/set by AMD-762TM sys. controller internal logic F = Performance enhancement set by BIOS E = Elective BIOS function 222 Recommended BIOS Settings Chapter 7 Preliminary Information 24462D--March 2002 AMD-762TM System Controller Software/BIOS Design Guide Registers ----Bits 0x0x0x34h 31:8 7:0 0x0x0x44h 31:24 Description AGP/PCI Capabilities Pointer Reserved Capabilities Pointer Extended BIU Control Reserved Speculative Read Data Movement Enable (Processor 1) 0000 - function disabled 0001 - once clock --1111 - fifteen clocks Speculative Read Data Movement Enable (Processor 0)' 0000 - function disabled 0001 - once clock --1111 - fifteen clocks Reserved P1_WrDataDly P0_WrDataDly Defer Write Data Movement Reserved P0_2BitPF P0_2BitPF Reserved ECC Mode/Status Reserved SERR_Enable Reserved ECC_Diag Initialized/ Required Value Actual Value Key fcn( ) Notes 000000h A0h r r AGP function pointer First item in AGP capabilities list 0h r 23:20 0000b 19:16 0000b 15:14 13:11 10:8 7 6:5 4 3 2:0 0x0x0x48h 31:16 15:14 13 12 KEY: yyyb yyyb 0b 0b 1b 1b 0b 0000h xxb 0b 0b r r r B r B B B r B r B From SIP stream From SIP stream Must be set for AMD AthlonTM processor Must be set for AMD Athlon processor Must be set by BIOS 00b = ECC/SERR Disabled 1xb = SERR on Multi_Bit Errors x1b = SERR on Single Bit Errors See SERR# 0x0x0x4[8] 0 = Disable, 1= Enable B= Mandatory BIOS function A= AGP setup by BIOS P= Power management setup by BIOS o = Setup by OS or OS driver r = Hardcoded and reserved u = PCI operational user interface c = Calculated/set by AMD-762TM sys. controller internal logic F = Performance enhancement set by BIOS E = Elective BIOS function Chapter 7 Recommended BIOS Settings 223 Preliminary Information AMD-762TM System Controller Software/BIOS Design Guide 24462D--March 2002 ECC_Mode 11:10 SPD # 11 xxb B SPD 9:8 ECC_Status 00b B 7:4 3:0 KEY: ECC_CS_MED ECC_CS_SED yh yh c c 00b = NO ECC or ECC Disabled 01b = Data Errors Reported 10b = Data Errors Corrected for Memory and PCI /AGP 11b = Data Errors Corrected and Memory Scrubbed 00b = No Error x1b =MED Multi Bit Error Detect 1xb =SED Single Bit Error Detect R/W/1C CS of first MED CS of first SED B= Mandatory BIOS function A= AGP setup by BIOS P= Power management setup by BIOS o = Setup by OS or OS driver r = Hardcoded and reserved u = PCI operational user interface c = Calculated/set by AMD-762TM sys. controller internal logic F = Performance enhancement set by BIOS E = Elective BIOS function 224 Recommended BIOS Settings Chapter 7 Preliminary Information 24462D--March 2002 AMD-762TM System Controller Software/BIOS Design Guide Registers ----Bits 0x0x0x4Ch 31:01 10 Description PCI Control Reserved PCI_66CLK2 Disable 0 = enabled 1= disabled PCI_66CLK1 Disable 0 = enabled 1= disabled PCI_66CLK0 Disable 0 = enabled 1= disabled Reserved M66EN 0 = 33 MHz PCI Bus 1= 66 MHz PCI Bus Reserved PCI_DT_En Initialized/ Required Value 0000h X Actual Value Key fcn( ) Notes r Should be set to enable clock to slot 2 on 66 MHz platforms. Should be set to enable clock to slot 1 on 66 MHz platforms. Should be set to enable clock to Southridge on 66 MHz platforms. r r B B When configured for 66 MHz PCI Bus this status bit will be zero if a 33 MHz card is installed Must be set by BIOS 0= Disable Delayed Transactions 1= Enable Delayed Transactions 0= Disable Ordering Rules Compliance 1 = Enable PCI Ordering Rules Compliance 1= Enable 0x0x1xRR Access 9 X 8 7:6 5 4:3 2 X 0 X 00b 0b 1 0 KEY: PCI_OR_EN Func1_En 0b 0b B B B= Mandatory BIOS function A= AGP setup by BIOS P= Power management setup by BIOS o = Setup by OS or OS driver r = Hardcoded and reserved u = PCI operational user interface c = Calculated/set by AMD-762TM sys. controller internal logic F = Performance enhancement set by BIOS E = Elective BIOS function Chapter 7 Recommended BIOS Settings 225 Preliminary Information AMD-762TM System Controller Software/BIOS Design Guide 24462D--March 2002 0x0x0x50h 31:24 23:20 19:16 15:12 11:8 7:5 4 3:0 KEY: AMD AthlonTM Processor System Bus Dynamic Compensation Reserved PVal NVal Byp_P Byp_N SlewCntl Byp Reserved 00h yh yh 0h 0h 011b 0b 0h r c c B B B B r P Transistor Value in Use N Transistor Value in Use P Transistor Value Used if Byp = 1 N Transistor Value Used if Byp = 1 1 = Enable Byp_P and Byp_N B= Mandatory BIOS function A= AGP setup by BIOS P= Power management setup by BIOS o = Setup by OS or OS driver r = Hardcoded and reserved u = PCI operational user interface c = Calculated/set by AMD-762TM sys. controller internal logic F = Performance enhancement set by BIOS E = Elective BIOS function 226 Recommended BIOS Settings Chapter 7 Preliminary Information 24462D--March 2002 AMD-762TM System Controller Software/BIOS Design Guide Registers ----Bits 0x0x0x54h 31 30 29 28 27 26 25:24 Description SDRAM Timing SPBWaitState AddrTiming_A SPD # 21 AddrTiming_B SPD # 21 RD_Wait_State Reg_DIMM_En SPD # 21 tWTR = Write Data In to Read Command Delay tWR = Write Recovery Time tRRD = Active Bank A to Initialized/ Required Value Actual Value Key fcn( ) Notes xb 1b 1b 1b 1b 1b 10b B B B B B B B FSB SPD SPD 0 @ 100-MHz FSB 1 @ 133-MHz FSB 1 @ Registered DIMM 1 @ Registered Must = 1 SPD 1 @ Registered DIMM 0 = 1 Clock 1 = 2 Clocks 00b=1 Clock, 01b=Reserved 10b=2 Clocks, 11b=3 Clocks 23 22:19 18:16 Delay SPD # 28 Reserved Active Bank Command xb 000_0b 001b B r B SPD 0 = 2 Clocks 1 = 3 Clocks Idle cycle to wait before pre-charging the idle bank Include bit 24 above Page Hit request before a nonPage hit Reserved tRC = Bank Cycle Time tRAS + tRP or SPD# 41(new, not yet implemented) tRP = Precharge Time SPD # 27 15:14 13:12 11:9 10b 00b xxxb B r B FSB and SPD FSB SPD 000 = 0 cyc, 001 = 8 cyc (safe) 010 = 12 cyc, 011 = 16 cyc 100 = 24 cyc, 101 = 32 cyc 110 = 48 cyc, 111 = Disable 00 = 1 cyc, 01 = 4 cyc 10 = 8 cyc (safe), 11 = 16 cyc 000 = 3 cyc, 001 = 4 cyc 010 = 5 cyc, 011 = 6 cyc 100 = 7 cyc, 101 = 8 cyc (safe) 110 = 9 cyc, 111 = 10 cyc 00 = 3 cyc (safe), 01 = 2 cyc 10 = 1 cyc, 11 = 4 cyc 8:7 KEY: xxb B B= Mandatory BIOS function A= AGP setup by BIOS P= Power management setup by BIOS o = Setup by OS or OS driver r = Hardcoded and reserved u = PCI operational user interface c = Calculated/set by AMD-762TM sys. controller internal logic F = Performance enhancement set by BIOS E = Elective BIOS function Chapter 7 Recommended BIOS Settings 227 Preliminary Information AMD-762TM System Controller Software/BIOS Design Guide 24462D--March 2002 Registers ----Bits 0x0x0x54h Description SDRAM Timing tRAS = Minimum Bank Active Time SPD # 30 tCL = CAS Latency Initialized/ Required Value Actual Value Key fcn( ) Notes 6:4 xxxb B FSB and SPD 000 = 2 cyc, 001 = 3 cyc 010 = 4 cyc, 011 = 5 cyc 100 = 6 cyc 101 = 7 cyc (safe) 110 = 8 cyc, 111 = 9 cyc 00 = 3 cyc (optional on DIMM, not recommended) 01 = 2 cyc, recommended 10 = 2.5 cyc, 11-reserved 00 = 1 cyc, 01 = 2 cyc 10 = 3 cyc (safe), 11 = 4 cyc 3:2 SPD # 25 or # 23 or #9 tRCD -- RAS to CAS Latency SPD # 29 xxb B FSB and SPD FSB and SPD 1:0 xxb B KEY: B= Mandatory BIOS function A= AGP setup by BIOS P= Power management setup by BIOS o = Setup by OS or OS driver r = Hardcoded and reserved u = PCI operational user interface c = Calculated/set by AMD-762TM sys. controller internal logic F = Performance enhancement set by BIOS E = Elective BIOS function 7.1.1 Example Settings for Memory Timing The following table provides example BIOS settings for the DRAM Timing register, for both 100-MHz and 133-MHz bus speeds. Note also that SPD values observed to date are from production DIMMs. Future additions and changes to the SPD bytes should be expected. 228 Recommended BIOS Settings Chapter 7 Preliminary Information 24462D--March 2002 AMD-762TM System Controller Software/BIOS Design Guide 0x0x0x54h 31 30 29 28 27 26 25:24 23 22:19 18:16 SDRAM Timing SPBWaitState AddrTiming_A SPD # 21 AddrTiming_B, SPD # 21 RD_Wait_State Reg_DIMM_En, SPD # 21 tWTR = Write Data In to Read CMD tWR = Write Recovery Time tRRD =ActBnkAtoActBnk CMD SPD # 28 100 MHz 0b 1b 1b 1b 1b 1b 10b 0b 0000b 133 MHz 1b 1b 1b 1b 1b 1b 10b 0b 0000b 001b SPD ns 0 @ 100 MHz , 1 @ 133 MHz FSB 1 @ Reg DIMM 1 @ Reg DIMM Must = 1 1 @ Reg DIMM 0 = 1 Clock, 1 = 2 Clocks 00b=1 Clock, 01b=Reserved 10b=2 Clocks, 11b=3 Clocks 3Ch 15 0 = 2 Clocks, 1 = 3 Clocks Idle cycle to wait before precharging the idle bank Page Hit request before a nonPage hit tRC = Bank Cycle Time 001b 15:14 13:12 11:9 10b 00b 10b 00b 110b to 111b 00b 100b to 101b ------01b --00b-10b 10b 41h to 46h 50h 2Dh to 32h 65 to 70 20 45 to 50 000 = 0 cyc, 001 = 8 cyc (safe) 010 = 12 cyc, 011 = 16 cyc 100 = 24 cyc, 101 = 32 cyc 110 = 48 cyc, 111 = Disable 00 = 1 cyc, 01 = 4 cyc 10 = 8 cyc, (safe) 11 = 16 cyc 000 = 3 cyc, 001 = 4 cyc 010 = 5 cyc, 011 = 6 cyc 100 = 7 cyc, 101 = 8 cyc (safe) 110 = 9 cyc, 111 = 10 cyc 00 = 3 cyc (safe), 01 = 2 cyc 10 = 1 cyc, 11 = 4 cyc 000 = 2 cyc, 001 = 3 cyc 010 = 4 cyc, 011 = 5 cyc 100 = 6 cyc, 101 = 7 cyc (safe) 110 = 8 cyc, 111 = 9 cyc 00 = 3 cyc (optional on DIMM, not recommended) 01 = 2 cyc, recommended 10 = 2.5 cyc 11 = reserved (See 00 above.) 20 00 = 1 cyc, 01 = 2 cyc 10 = 3 cyc (safe), 11 = 4 cyc tRAS + tRP or SPD# 41(new, not yet implemented) tRP = Precharge Time SPD # 27 tRAS = Minimum Bank Active Time SPD # 30 tCL = CAS Latency 100b 8:7 01b 6:4 011b 3:2 SPD # 25 (Not Available) # 23 ---01b 01b 10b 10b 01b A0h 75h A0h 75h 50h #9 1:0 tRCD -- RAS to CAS Latency SPD # 29 Chapter 7 Recommended BIOS Settings 229 Preliminary Information AMD-762TM System Controller Software/BIOS Design Guide 24462D--March 2002 Registers ----Bits 0x0x0x58h 31 30 29 28 27 26 Description SDRAM Mode/Status Clk_Dis5 - DIMM Clock 5 Clk_Dis4 - DIMM Clock 4 Clk_Dis3 - DIMM Clock 3 Clk_Dis2 - DIMM Clock 2 Clk_Dis1 - DIMM Clock 1 Clk_Dis0 - DIMM Clock 0 Initialized/ Required value xb xb xb xb xb xb Actual Value Key fcn( ) Notes E E E E E E MB MB MB MB MB MB 25 SDRAM Init 1b B 0=Enable, 1=Disable 0=Enable, 1=Disable 0=Enable, 1=Disable 0=Enable, 1=Disable 0=Enable, 1=Disable 0=Enable, 1=Disable Set to start memory controller. All other memory config bits should be set before setting this bit. Stays set, can be reset but not to 0. To be set before or with SDRAM Init. Causes writing of the memory mode register when SDRAM Init is set. After setting, drops to 0 when function complete. Cannot be set to 0. Set <---> Last Power State 01b <---> MOFF, S4 or S5 10b <---> S3 Refer to "S3 Suspend to RAM State Requirements" on page 197 for details. 0-Disable, 1-Enable 1 = Disable Refresh = Debug Bit @100 MHz FSB: 00 = 2K cyc, 01 = 1.5K cyc 10 = 1K cyc, 11 = 0.75K cyc @133-MHz FSB: 00=1.5K cyc, 01=1.1K cyc 10=0.75K cyc, 11=0.37K cyc 24 Reserved 0b r 23 Mode register status xb B 22:21 STR_Control = Suspend to RAM Control xxb B 20 19 18 Burst refresh enable Ref_Dis = Refresh Disable Reserved 0b 0b 0b B B B FSB and SPD 17:16 Cycles per (between) Refresh SPD # 12 xxb B 15:8 KEY: 0_0h r c = Calculated/set by AMD-762TM sys. controller internal logic F = Performance enhancement set by BIOS E = Elective BIOS function B= Mandatory BIOS function A= AGP setup by BIOS P= Power management setup by BIOS o = Setup by OS or OS driver r = Hardcoded and reserved u = PCI operational user interface 230 Recommended BIOS Settings Chapter 7 Preliminary Information 24462D--March 2002 AMD-762TM System Controller Software/BIOS Design Guide Registers ----Bits 7 6 5 4 3 2 1 0 KEY: Description CS7_X4Mode Chip-Select x4 Enable SPD # 13 CS6_X4Mode Chip-Select x4 Enable SPD # 13 CS5_X4Mode Chip-Select x4 Enable SPD # 13 CS4_X4Mode Chip-Select x4 Enable SPD # 13 CS3_X4Mode Chip-Select x4 Enable SPD # 13 CS2_X4Mode Chip-Select x4 Enable SPD # 13 CS1_X4Mode Chip-Select x4 Enable SPD # 13 CS0_X4Mode Chip-Select x4 Enable SPD # 13 Initialized/ Required Value xb xb xb xb xb xb xb xb Actual Value Key B B B B B B B B fcn( ) SPD SPD SPD SPD SPD SPD SPD SPD Notes 0=x8/x16, 1=x4 DIMM devices 0=x8/x16, 1=x4 DIMM devices 0=x8/x16, 1=x4 DIMM devices 0=x8/x16, 1=x4 DIMM devices 0=x8/x16, 1=x4 DIMM devices 0=x8/x16, 1=x4 DIMM devices 0=x8/x16, 1=x4 DIMM devices 0=x8/x16, 1=x4 DIMM devices B= Mandatory BIOS function A= AGP setup by BIOS P= Power management setup by BIOS o = Setup by OS or OS driver r = Hardcoded and reserved u = PCI operational user interface c = Calculated/set by AMD-762TM sys. controller internal logic F = Performance enhancement set by BIOS E = Elective BIOS function Chapter 7 Recommended BIOS Settings 231 Preliminary Information AMD-762TM System Controller Software/BIOS Design Guide 24462D--March 2002 Registers ----Bits 0x0x0x60h 31 30:28 27:25 24:22 21:19 18 Description BIU0 Status/Control Probe enable for CPU0 Reserved Xca_Probe_Cnt Xca_RD_Cnt Xca_WR_Cnt AMD AthlonTM processor system bus halt disconnect enable Initialized/ Required Value 1b 000b 010b 110b 110b 0b Actual Value Key fcn( ) Notes B B B B B B 0=Disable, 1=Enable 17 AMD Athlon processor system bus stop grant disconnect enable Probe limit Ack limit 0000 = 1 un-acked command 0001 = 2....... Bypass_ En 0 = Super Bypass Disable 1 = Super Bypass Enable SysDC_Out_ delay SysDC_In_ delay WR2_RD RD2_WR BIU0 SIP ClkFwd Offset RO from Init/SIP logic 1b B 16:14 13:10 110b 0011b B r 9 8:7 6:3 2 1:0 0x0x0x64h 31 30:0 KEY: Xb yyb yyyyb yb yyb B r r r r 0=Disable 1=Enable Refer to "Power Management" on page 193 for details. 0=Disable, 1=Enable Refer to "Power Management" on page 193 for details. 0-7 = 1 to 8 probes 110b = 7 recommended This field should be used to set up SysAckLimit in AMD AthlonTM processor (+1 to this value) (SYSCFG) This feature can be enabled when only processor P0 is installed, it must be disabled at all other times. From init logic From init logic From init logic From init logic 0=Delay groups 1 and 3 1=No delays 0b yyyb yy_yyyyh B r B= Mandatory BIOS function A= AGP setup by BIOS P= Power management setup by BIOS o = Setup by OS or OS driver r = Hardcoded and reserved u = PCI operational user interface c = Calculated/set by AMD-762TM sys. controller internal logic F = Performance enhancement set by BIOS E = Elective BIOS function 232 Recommended BIOS Settings Chapter 7 Preliminary Information 24462D--March 2002 AMD-762TM System Controller Software/BIOS Design Guide 0x0x0x68h 31 30:28 27:25 21:19 18 BIU1 Status/Control Probe enable for CPU1 Reserved Xca_Probe_Cnt Xca_WR_Cnt AMD AthlonTM processor system bus halt disconnect enable 1b 000b 010b 110b 0b B B B B B 0=Disable, 1=Enable 17 AMD Athlon processor system bus stop grant disconnect enable Probe limit Ack limit 0000 = 1 un-acked command 0001 = 2....... Reserved SysDC_Out_ delay SysDC_In_ delay WR2_RD RD2_WR BIU1 SIP ClkFwd Offset RO from Init/SIP logic 1b B 16:14 13:10 9 8:7 6:3 2 1:0 0x0x0x6Ch 31 30:0 KEY: 110b 0011b 0b yyb yyyyb yb yyb B r r r r r r 0=Disable 1=Enable Refer to "Power Management" on page 193 for details. 0=Disable, 1=Enable Refer to "Power Management" on page 193 for details. 0-7 = 1 to 8 probes 110b = 7 recommended This field should be used to set up SysAckLimit in AMD AthlonTM processor (+1 to this value) (SYSCFG) From init logic From init logic From init logic From init logic 0=Delay groups 1 and 3 1=No delays 0b yyyb yy_yyyyh B r B= Mandatory BIOS function A= AGP setup by BIOS P= Power management setup by BIOS o = Setup by OS or OS driver r = Hardcoded and reserved u = PCI operational user interface c = Calculated/set by AMD-762TM sys. controller internal logic F = Performance enhancement set by BIOS E = Elective BIOS function Chapter 7 Recommended BIOS Settings 233 Preliminary Information AMD-762TM System Controller Software/BIOS Design Guide 24462D--March 2002 Registers ----Bits 0x0x0x70h 31:19 18 17:11 10 Description MRO Status/Control Reserved Self_Ref_En Reserved PCI pipe enable Initialized/ Required Value 0b 1b 0000000b 1b Actual Value Key fcn( ) Notes r B B B 0 = MRO checks outstanding read probe before PCI transactions 1 = MRO pipelines PCI transactions 0 = BIU does RID/INV probes, forcing MRO MWQ to wait for data movement 1 = BIU does NOP/INV probes for PCI full-block writes Enable memory self refresh for S1/S3 states. 9 8:0 0X0X0X80h 31:20 19 18 17 16 15:8 7:0 KEY: PCI Block Write Enable Reserved Who AM I Reserved I Read WHAMI Processor 1 I Read WHAMI Processor 0 BIU1 present BIU0 present First AMD Athlon system bus ID Who AM I 00b 1b 000h 000h Xb Xb Xb Xb Xh Xh B B r c c c c c c Set when processor P1 has read WHAMI register Set when processor P0 has read WHAMI register Set when processor P1 is installed Set when processor P1 is installed 01 = Processor P1 00 = Processor P0 Returns ID of processor currently reading WHAMI c = Calculated/set by AMD-762TM sys. controller internal logic F = Performance enhancement set by BIOS E = Elective BIOS function B= Mandatory BIOS function A= AGP setup by BIOS P= Power management setup by BIOS o = Setup by OS or OS driver r = Hardcoded and reserved u = PCI operational user interface 234 Recommended BIOS Settings Chapter 7 Preliminary Information 24462D--March 2002 AMD-762TM System Controller Software/BIOS Design Guide Registers ----Bits 0x0x0x84h Description PCI Arbitration Control Initialized/ Required Value Actual Value Key fcn() Notes 31:24 AGP VGA BIOS address decode 0Fh A 23 22:18 17 16 Tgt_Latency Reserved AGP Chaining PCI Chaining 0b 000_00b 1b 1b B r B B 0x0x0 x84[3] System config dependent Bit 31: 0D_C000 = 0D_FFFF Bit 30: 0D_8000 = 0D_BFFF ... Bit 24: 0C_0000 = 0C_3FFF One or more of these bits should be set if an AGP card has a ROM BIOS. 0=AMD-751TM System Controller-Compatible 1=PCI Maximum Target Latency Rule. When =1, 0x0x0x84[3] must = 0. Enabled = 1, when set CPU writes to AGP are chained Enabled = 1, when set CPU writes to PCI are chained Enabled = 1, allows monochrome adapter for AGP device driver debug. Normally 0. See AMD-762TM System Controller Data Sheet, order# 24461, for information. 1 = Enables retry on PCI if there are pending posted writes 1 = Enables retry on AGP if there are pending posted writes 0 = Returns read data error to processor on master abort or target abort 1 = AMD-762 system controller returns all 1s on data read error 15 MDA Support 0b A 14 13 PCI Write-Post retry AGP Write Post retry 1b 1b B B 12 Dis Rd Data Err 1b B KEY: B= Mandatory BIOS function A= AGP setup by BIOS P= Power management setup by BIOS o = Setup by OS or OS driver r = Hardcoded and reserved u = PCI operational user interface c = Calculated/set by AMD-762TM sys. controller internal logic F = Performance enhancement set by BIOS E = Elective BIOS function Chapter 7 Recommended BIOS Settings 235 Preliminary Information AMD-762TM System Controller Software/BIOS Design Guide 24462D--March 2002 Registers ----Bits 11 10 9 8 7 6 5 Description Dis AGP Early Probe Dis PCI Early Probe Dis AGP arbiter pipelining Southbridge lock disable PM register enable 15-Mbytes hole enable 14-Mbytes hole enable Initialized/ Required Value 0b 0b 0b 0b xb xb xb Actual Value Key A B A B P B B fcn( ) Notes 1 = Disable early snoop from AGP master running a PCI cycle to memory 1 = Disable early probe request for write cycles from an external PCI master 1 = Disable AGP arbiter from pipelining grants onto bus 1 = Disable flushing function performed before granting bus to the Southbridge 1 = Enables R/W accesses to PM register at 0:0x18 BAR2 - AGP Power management 1 = Enable a memory hole at 15-16 Mbytes 1 = Enable a memory hole at 14-15 MBytes 1 = Enable PCI decoding in EV6 mode. Used for opening buffers in 640K to 1-Mbyte memory address space. Legacy USB/SCSI devices sometimes need this capability. 1 = Disable AMD-762TM system controller target latency timer on both PCI and AGP's PCI interfaces 1 = Disables AMD-762 system controller to prefetch data from SDRAM when a PCI master on AGP bus reads from main memory 1 = Enables AMD-762 system controller to prefetch data from SDRAM when a PCI master on PCI bus reads from main memory 0 = PCI arbiter parks on processor accesses to PCI 1 = Enables parking on an external PCI master 4 EV6 mode 1b B 3 Target latency timer disable 1b B 0x0x 0x84 [23] 2 ApcPreEn 0b B 1 PciPreEn 0b B 0 ParkPCI 0b B KEY: B= Mandatory BIOS function A= AGP setup by BIOS P= Power management setup by BIOS o = Setup by OS or OS driver r = Hardcoded and reserved u = PCI operational user interface c = Calculated/set by AMD-762TM sys. controller internal logic F = Performance enhancement set by BIOS E = Elective BIOS function 236 Recommended BIOS Settings Chapter 7 Preliminary Information 24462D--March 2002 AMD-762TM System Controller Software/BIOS Design Guide Registers ---Bits 0x0x0x88h 31:29 28:26 25 24 23 22 Description Config Status AGP_Clk_Mux Sys_Clk_Mux Type_Det S2K_Thresh K7_PP_En IG_PP_En Initialized/ Required Value yyyb yyyb yb yb 1b 1b Actual Value Key fcn( ) Notes r r r r r r FSB speed: 00b=100 MHz 01b=66 MHz 10b= Reserved 11b=133 MHz 0=1.5-V AGP Card Signalling 1=3.3-V AGP Card Signalling 21:20 Clk_Speed yyb r 19:18 17:16 15 14 13 12 11:8 7 6 5 4 3:0 0x0x0x9Ch 31:24 23:0 KEY: Reserved S2K_Bus_Len Tristate_En Nand_En Bypass_PLLs Dis_Divider Reserved Sip_ROM Reg_DIMM_En In_Clk_En Out_Clk_En CPU0_Divider PCI Top of Memory PCI Memory Top Reserved yyb yyb yb yb yb yb yh yb 1b yb yb yh r r r r r r r r r r r r Actual Memory Size AD[31:24] xxh 000_0000h B r B= Mandatory BIOS function A= AGP setup by BIOS P= Power management setup by BIOS o = Setup by OS or OS driver r = Hardcoded and reserved u = PCI operational user interface c = Calculated/set by AMD-762TM sys. controller internal logic F = Performance enhancement set by BIOS E = Elective BIOS function Chapter 7 Recommended BIOS Settings 237 Preliminary Information AMD-762TM System Controller Software/BIOS Design Guide 24462D--March 2002 Registers ---Bits 0x0x0xA0h 31:24 23:20 19:16 15:8 7:0 0x0x0xA4h 31:24 23:10 9 8:6 5 4 3 2:0 0x0x0xA8h 31:10 9 Description AGP Capability Identifier Reserved Major_Rev Minor_Rev Next_Pointer Cap_ID AGP Status Register Max_ReqQ_Depth Reserved SBA Reserved R4G FW Reserved Rates AGP Command Register Reserved SBA_Ena Sideband addressing enable AGP_Ena AGP operation enable Reserved Greater than 4G address support Fast_Writes Reserved AGP data transfer mode Initialized/ Required Value 00h 2h 0h 00h 02h 0Fh 00b 000h 1b 000b 0b yb 0b 111b 0000_0h 00b yb Actual Value Key r r r r r r r r r r r r r fcn( ) Notes Null = Final item on list 02h = AGP Max # AGP Command Requests Side Band Addressing Supported Fixed at 4 Gbytes Maximum 1 = Fast Write Support 0 = Fast Write Not Supported AMD-762TM system controller supports 1x/2x/4x 0x0x 0B4 [7] r o Set by operating system agent, not BIOS. 0 = Disable, 1 = Enable Set by operating system agent, not BIOS. 0 = Disable, 1 = Enable 0 = Disable, 1 = Enable 0x0x0 B4[7] 0=Disabled, 1=Enabled 001b=1x, 010b=2x,100b=4x c = Calculated/set by AMD-762TM sys. controller internal logic F = Performance enhancement set by BIOS E = Elective BIOS function 8 7:6 5 4 3 2:0 KEY: yb 0b 0b yb 0b yyyb o r r o r o B= Mandatory BIOS function A= AGP setup by BIOS P= Power management setup by BIOS o = Setup by OS or OS driver r = Hardcoded and reserved u = PCI operational user interface 238 Recommended BIOS Settings Chapter 7 Preliminary Information 24462D--March 2002 AMD-762TM System Controller Software/BIOS Design Guide Registers ----Bits 0x0x0xACh 31:17 16 15:4 Description AGP Virtual Address Space Size Register Reserved VGA_IA_En Reserved Initialized/ Required Value Actual Value Key fcn( ) Notes yyyb 000h xb 000h r B r 000 = 32 Mbytes 001 = 64 Mbytes 010 = 128 Mbytes 011 = 256 Mbytes 100 = 512 Mbytes 101 = 1 Gbyte 110 = 2 Gbytes 128 Mbytes recommended 0 = Disable register 1 = Enable register 0:0x10 (BAR0) and start GART 0 = No ISA aliasing on address [15:0] 1 = Force AMD-762TM system controller to alias ISA address [15:0] 3:1 VA_Size AGP aperture size xxxb A 0 0x0x0xB0h 31:21 20 19 18 17 16 15:0 KEY: GARTEna AGP aperture base address enable Gart/AGP Mode Control Reserved Reserved NonGART Snoop Reserved GART page directory cache enable GART Index Scheme control Reserved xb A 00h 000b 0b 0b 0b 0b yb 00h r B B B B o r Debug/Performance register 0 = Disable, 1 = Enable 0 = 2-Level, 1 = 1-Level Mode Debug/Performance register 0 = Disable probes 1 = Enable probes B= Mandatory BIOS function A= AGP setup by BIOS P= Power management setup by BIOS o = Setup by OS or OS driver r = Hardcoded and reserved u = PCI operational user interface c = Calculated/set by AMD-762TM sys. controller internal logic F = Performance enhancement set by BIOS E = Elective BIOS function Chapter 7 Recommended BIOS Settings 239 Preliminary Information AMD-762TM System Controller Software/BIOS Design Guide 24462D--March 2002 Registers ----Bits 0x0x0xB4h 31:28 27:24 23 22 21:16 15:8 PVal NVal Reserved DisStrb Description AGP 4x Dynamic Compensation Initialized/ Required Value Actual Value Key fcn( ) Notes yh yh 0b 0b 000001b 00h c c r A A r P transistor strength, xfer I/O pads N transistor strength, xfer I/O pad 1=Disable ADSTB[1:0}# 100-ms intervals for Always_Compensate 0=Disable, 1=Enable Controls 0x0x0xA4h[4] and 0x0x0xA8h[4] Refer to "Feature Override Bits for AGP Cards" on page 216 for details. 0=Disabled, 1=Enabled -> Forces 0x0x0xA4h[0]->010b->2x AGP Refer to "Feature Override Bits for AGP Cards" on page 216 for details. Do_Compensate=1 shows PVal and NVal when Comp3.3 =1 with 3.3-V AGP cards Normally = 0 0=Disable, 1=Enable Refer to "AGP Interface" on page 213 for details. Set to init dynamic compensation Clears when finished Quantum_Cnt Reserved 7 FW_Enable xb A B4/BF 6 4x_Override xb A B4/BF 5 4:3 2 1 Comp3.3 Reserved PCI drive strength Always_Compensate 0b 0b 0b xb A r A A B4/BB 0 Do_Compensate 0b A KEY: B= Mandatory BIOS function A= AGP setup by BIOS P= Power management setup by BIOS o = Setup by OS or OS driver r = Hardcoded and reserved u = PCI operational user interface c = Calculated/set by AMD-762TM sys. controller internal logic F = Performance enhancement set by BIOS E = Elective BIOS function 240 Recommended BIOS Settings Chapter 7 Preliminary Information 24462D--March 2002 AMD-762TM System Controller Software/BIOS Design Guide Registers ----Bits 0x0x0xB8h 31:28 Description AGP Compensation Bypass BYP_PDrvXfer Initialized/ Required Value Actual Value Key fcn( ) Notes xh A B4/BB 27:24 BYP_NDrvXfer xh A B4/BB 23 22:20 19:18 BYPXfer Reserved BYP_PSlewXfer xb 000b xxb A r A B4/BB P Drive bypass value for data Refer to "BIOS Initialization Requirements" on page 217 for details. N Drive bypass value for data Refer to "BIOS Initialization Requirements" on page 217 for details. 1=Enable Drive Bypass for Data Refer to "BIOS Initialization Requirements" on page 217 for details. P slew rate value for data Refer to "BIOS Initialization Requirements" on page 217 for details. N slew rate value for data Refer to "BIOS Initialization Requirements" on page 217 for details. P drive bypass value for strobes Refer to "BIOS Initialization Requirements" on page 217 for details. N drive bypass value for strobes Refer to "BIOS Initialization Requirements" on page 217 for details. B4/BB 17:16 BYP_NSlewXfer xxb A B4/BB 15:12 BYP_PDrvStrb xh A B4/BB 11:8 BYP_NDrvStrb xh A B4/BB KEY: B= Mandatory BIOS function A= AGP setup by BIOS P= Power management setup by BIOS o = Setup by OS or OS driver r = Hardcoded and reserved u = PCI operational user interface c = Calculated/set by AMD-762TM sys. controller internal logic F = Performance enhancement set by BIOS E = Elective BIOS function Chapter 7 Recommended BIOS Settings 241 Preliminary Information AMD-762TM System Controller Software/BIOS Design Guide 24462D--March 2002 Registers ----Bits 7 6:4 3:2 BYPStrb Reserved Description Initialized/ Required Value xb 000b xxb Actual Value Key fcn( ) Notes 1=Enable Drive Bypass for Strobes Refer to "BIOS Initialization Requirements" on page 217 for details. P slew rate value for strobes Refer to "BIOS Initialization Requirements" on page 217 for details. N slew rate value for strobes Refer to "BIOS Initialization Requirements" on page 217 for details. A r A B4/BB BYP_PSlewStrb B4/BB 1:0 BYP_NSlewStrb xxb A B4/BB KEY: B= Mandatory BIOS function A= AGP setup by BIOS P= Power management setup by BIOS o = Setup by OS or OS driver r = Hardcoded and reserved u = PCI operational user interface c = Calculated/set by AMD-762TM sys. controller internal logic F = Performance enhancement set by BIOS E = Elective BIOS function 242 Recommended BIOS Settings Chapter 7 Preliminary Information 24462D--March 2002 AMD-762TM System Controller Software/BIOS Design Guide 7.1.2 TYPEDET# 0x0x0x88[25] Examples: AGP Compensation Register Settings (0xB4-0xBB) Type_Det = 1 indicates that a card in the AGP slot is a 3.3-V signalling card, which supports 2X AGP maximum. A 3.3-V signalling card cannot run above 2X AGP. Type_Det = 0 indicates that a card in the AGP slot is a 1.5-V signalling card, which supports 4X AGP maximum. A 1.5-V signalling card can run at 1X, 2X, or 4X AGP rates. Refer to "AGP Interface" on page 213 for details on how the value of the Type_Det bit and the settings of the AGP c o m p e n s a t i o n re g i s t e r a f f e c t t h e s e t t i n g s i n AG P Compensation Bypass register. Type_Det = 1 2X AGP Maximum Type_Det =1 == 3.3-V card in AGP slot 0x0x0x.. B4h 48h B5h 00h B6h 01h B7h C5h B8h 0Fh B9h FFh BAh 0Fh BBh C5h No Option Type_Det = 0 4X AGP Maximum, Reduced to 2X AGP with 4X_Override 0x0x0x.. B4h 4Ah B5h 00h B6h 01h B7h D8h B8h 8Fh B9h FFh BAh 04h BBh D8h Option 1 4x_Override and Always_Compensate Option 2 0x0x0x.. B4h 48h B5h 00h B6h 01h B7h D8h B8h 8Fh B9h FFh BAh 84h BBh D8h 4x_Override and Bypass Type_Det = 0 4xAGP Maximum, Options of Always Compensate, Bypass and Fast Writes 0x0x0x.. B4h 02h 0x0x0x.. B4h 82h 0x0x0x.. B4h 00h 0x0x0x.. B4h 80h B5h 00h B5h 00h B5h 00h B5h 00h B6h 01h B6h 01h B6h 01h B6h 01h B7h D8h B7h D8h B7h D8h B7h D8h B8h 8Fh B8h 8Fh B8h 8Fh B8h 8Fh B9h FFh B9h FFh B9h FFh B9h FFh BAh 04h BAh 04h BAh 84h BAh 84h BBh D8h BBh D8h BBh D8h BBh D8h Option 1 Always_Compensate Option 2 Always Compensate and Fast Writes Option 3 Bypass Option 4 Bypass and Fast Writes Chapter 7 Recommended BIOS Settings 243 Preliminary Information AMD-762TM System Controller Software/BIOS Design Guide 24462D--March 2002 Registers ----Bits 0x0x0xC0h Description Memory Base Address Register 0 CS_Base Chip-Select Base 0 Bank 0 base address Starting address of the bank Map to AD[31:23] Initialized/ Required Value Actual Value Key fcn( ) Notes 31:23 xxh xb B Set by memory sizing routines 0000_0000_0b = 0 0000_0001_0b = 16 Mbytes 0000_0010_0b = 32 Mbytes 0000_0011_0b = 48 Mbytes 0000_1000_0b = 128 Mbytes 0001_0000_0b = 256 Mbytes 0010_0000_0b = 512 Mbytes, etc. Set by memory sizing routines 0000_0000_1b = 16 Mbytes 0000_0001_1b = 32 Mbytes 0000_0011_1b = 64 Mbytes 0000_0111_1b = 128 Mbytes 0000_1111_1b = 256 Mbytes 0001_1111_1b = 512 Mbytes 0011_1111_1b = 1 Gbyte 0111_1111_1b = 1 Gbyte SPD # 31 and 13 01b=SDRAM device <256 Mbits 10b=SDRAM device >128 Mbits 00b and 11b are reserved 0=Disable CS, 1=Enable CS 22:16 Reserved 000b 0h r 15:7 CS_Mask Chip-Select Mask 0 Bank 0 address mask Sizes the bank Map to AD[31:23] xxh xb B 6:3 Reserved Addr_Mode Size of Device = Size of Bank x (Primary SDRAM Width /8) Enable/Disable Bank 1 Memory Base Address Register 1 Chip-Select Base 1 Reserved Chip-Select Mask 1 Reserved Addr_Mode Enable/Disable Bank 1 0h r 2:1 xxb B 0 0x0x0xC4h 31:23 22:16 15:7 6:3 2:1 0 KEY: xb B xxh xb 000b 0h xxh xb 0h xxb xb B r B r B B As 0x0x0xC0h above As 0x0x0xC0h above As 0x0x0xC0h above As 0x0x0xC0h above As 0x0x0xC0h above As 0x0x0xC0h above B= Mandatory BIOS function A= AGP setup by BIOS P= Power management setup by BIOS o = Setup by OS or OS driver r = Hardcoded and reserved u = PCI operational user interface c = Calculated/set by AMD-762TM sys. controller internal logic F = Performance enhancement set by BIOS E = Elective BIOS function 244 Recommended BIOS Settings Chapter 7 Preliminary Information 24462D--March 2002 AMD-762TM System Controller Software/BIOS Design Guide Registers ----Bits 0x0x0xC8h 31:23 22:16 15:7 6:3 2:1 0 0x0x0xCCh 31:23 22:16 15:7 6:3 2:1 0 KEY: Description Memory Base Address Register 2 Chip-Select Base 2 Reserved Chip-Select Mask 2 Reserved Addr_Mode Enable/Disable Bank 2 Memory Base Address Register 3 Chip-Select Base 3 Reserved Chip-Select Mask 3 Reserved Addr_Mode Enable/Disable Bank 3 Initialized/ Required Value Actual Value Key fcn( ) Notes xxh xb 000b 0h xxh xb 0h xxb xb B r B r B B As 0x0x0xC0h above As 0x0x0xC0h above As 0x0x0xC0h above As 0x0x0xC0h above As 0x0x0xC0h above As 0x0x0xC0h above xxh xb 000b 0h xxh xb 0h xxb xb B r B r B B As 0x0x0xC0h above As 0x0x0xC0h above As 0x0x0xC0h above As 0x0x0xC0h above As 0x0x0xC0h above As 0x0x0xC0h above B= Mandatory BIOS function A= AGP setup by BIOS P= Power management setup by BIOS o = Setup by OS or OS driver r = Hardcoded and reserved u = PCI operational user interface c = Calculated/set by AMD-762TM sys. controller internal logic F = Performance enhancement set by BIOS E = Elective BIOS function Memory Rules 1. Memory must be organized so that the largest banks occupy the lowest addresses. 2. Note that to accommodate ACPI S3 state (Suspend to RAM), some bits related to memory control are not initialized at reset time. All of these bits must be initialized by BIOS for proper operation. This action should be done prior to attempting DRAM access. 3. Registered memories can be configured four deep. In all cases, unused memory registers must be zeroed. Chapter 7 Recommended BIOS Settings 245 Preliminary Information AMD-762TM System Controller Software/BIOS Design Guide 24462D--March 2002 Registers ----Bits 0x0x0xD0h 31:23 22:16 15:7 6:3 2:1 0 0x0x0xD4h 31:23 22:16 15:7 6:3 2:1 0 0x0x0xD8h 31:23 22:16 15:7 6:3 2:1 0 0x0x0xDCh 31:23 22:16 15:7 6:3 2:1 0 KEY: Description Memory Base Address Register 4 Chip-Select Base 4 Reserved Chip-Select Mask 4 Reserved Addr_Mode Enable/Disable Bank 4 Memory Base Address Register 5 Chip-Select Base 5 Reserved Chip-Select Mask 5 Reserved Addr_Mode Enable/Disable Bank 5 Memory Base Address Register 6 Chip-Select Base 6 Reserved Chip-Select Mask 6 Reserved Addr_Mode Enable/Disable Bank 6 Memory Base Address Register 7 Chip-Select Base 7 Reserved Chip-Select Mask 7 Reserved Addr_Mode Enable/Disable Bank 7 Initialized/ Required Value xxh xb 000b 0h xxh xb 0h xxb xb xxh xb 000b 0h xxh xb 0h xxb xb xxh xb 000b 0h xxh xb 0h xxb xb xxh xb 000b 0h xxh xb 0h xxb xb Actual Value Key fcn( ) Notes B r B r B B B r B r B B B r B r B B B r B r B B As 0x0x0xC0h above As 0x0x0xC0h above As 0x0x0xC0h above As 0x0x0xC0h above As 0x0x0xC0h above As 0x0x0xC0h above As 0x0x0xC0h above As 0x0x0xC0h above As 0x0x0xC0h above As 0x0x0xC0h above As 0x0x0xC0h above As 0x0x0xC0h above As 0x0x0xC0h above As 0x0x0xC0h above As 0x0x0xC0h above As 0x0x0xC0h above As 0x0x0xC0h above As 0x0x0xC0h above As 0x0x0xC0h above As 0x0x0xC0h above As 0x0x0xC0h above As 0x0x0xC0h above As 0x0x0xC0h above As 0x0x0xC0h above B= Mandatory BIOS function A= AGP setup by BIOS P= Power management setup by BIOS o = Setup by OS or OS driver r = Hardcoded and reserved u = PCI operational user interface c = Calculated/set by AMD-762TM sys. controller internal logic F = Performance enhancement set by BIOS E = Elective BIOS function 246 Recommended BIOS Settings Chapter 7 Preliminary Information 24462D--March 2002 AMD-762TM System Controller Software/BIOS Design Guide 7.1.3 PCI Bus 0, Device 0, Function 1 Registers The Device 0, Function 1 registers are used for the purpose of controlling the DDR SDRAM interface drive strengths, and calibration of the Programmable Delay Lines (PDLs). All Function 1 register bits are defaulted to an unknown value as required for the AMD-762 system controller to support the Advanced Configuration and Power Interface (ACPI) S3 (Suspend to RAM) state. For proper operation, it is absolutely necessary that BIOS initialize all Function 1 register bits. Please obtain the AMD-762TM System Controller Revision Guide, order# 24089, for the most current information for each silicon revision. Chapter 7 Recommended BIOS Settings 247 Preliminary Information AMD-762TM System Controller Software/BIOS Design Guide 24462D--March 2002 Registers ----Bits 0x0x1x40h 31:8 7 Description DDR PDL Calibration Control Reserved SW_Recal Set after setting SW_Cal_Dly Use_Act_Dly Use Actual Delay Initialized/ Required Value 0000_000h 0b Actual Value Key fcn( ) Notes r B Write 1=>Calibration 0=Calibration Complete 1=Calibration Not Complete 0=Disable, 1=Enable SW_Recal and Auto_Cal_En Must = 0 When Use_Act_Dly = 1 0=Disable 1=Enable Refer to AMD-762TM System Controller Revision Guide, order# 24089, for special instructions for Revision B2 silicon. 0=Disable 1=Enable Refer to AMD-762TM System Controller Revision Guide, order# 24089, for special instructions for Revision B2 silicon. 00=10000 System Clocks 01=1000000 System Clocks 10=10000000 System Clocks 11=Reserved Half Period of the System Clock Delay for DQS: 100 MHz = 69h 133 MHz = 6Bh SW_Cal_Dly in # of Buffers From SW_Recal or Direct Write 6 0b B 5 Auto_Cal_En Auto Calibration Mode 1b B 4 Act_Dly_Inh Actual Delay Update Inhibit 0b B 3:2 1:0 Reserved Auto_Cal_Period Auto-Calibration Period DDR PDL Configuration Register 0 Clk_Dly SW_Cal_Dly Cal_Dly Act_Dly 00b 01b r B 0x0x1x44h 31:24 23:16 15:8 7:0 KEY: yyh xxh yyh xxh c B c c FSB B= Mandatory BIOS function A= AGP setup by BIOS P= Power management setup by BIOS o = Setup by OS or OS driver r = Hardcoded and reserved u = PCI operational user interface c = Calculated/set by AMD-762TM sys. controller internal logic F = Performance enhancement set by BIOS E = Elective BIOS function 248 Recommended BIOS Settings Chapter 7 Preliminary Information 24462D--March 2002 AMD-762TM System Controller Software/BIOS Design Guide Registers ----Bits 0x0x1x48h 31:24 23:16 15:8 7:0 0x0x1x4Ch 31:24 23:16 15:8 7:0 0x0x1x50h 31:24 Description DDR PDL Configuration Register 1 Clk_Dly SW_Cal_Dly Cal_Dly Act_Dly DDR PDL Configuration Register 2 Clk_Dly SW_Cal_Dly Cal_Dly Act_Dly DDR PDL Configuration Register 3 Clk_Dly Initialized/ Required Value yyh xxh yyh xxh yyh xxh yyh xxh yyh Actual Value Key c B c c c B c c c fcn( ) Notes Half Period of the System Clock Delay for DQS: 100 MHz = 69h 133 MHz = 6Bh SW_Cal_Dly in # of Buffers From SW_Recal or Direct Write Half Period of the System Clock Delay for DQS: 100 MHz = 69h 133 MHz = 6Bh SW_Cal_Dly in # of Buffers from SW_Recal or Direct Write Half Period of the System Clock Delay for DQS: 100 MHz = 69h 133 MHz = 6Bh SW_Cal_Dly in # of Buffers from SW_Recal or Direct Write Half Period of the System Clock Delay for DQS: 100 MHz = 69h 133 MHz = 6Bh SW_Cal_Dly in # of Buffers From SW_Recal or Direct Write Half Period of the System Clock Delay for DQS: 100 MHz = 69h 133 MHz = 6Bh SW_Cal_Dly in # of Buffers From SW_Recal or Direct Write FSB FSB 23:16 15:8 7:0 0x0x1x54h 31:24 SW_Cal_Dly Cal_Dly Act_Dly DDR PDL Configuration Register 4 Clk_Dly xxh yyh xxh yyh B c c c FSB 23:16 15:8 7:0 0x0x1x58h 31:24 23:16 15:8 7:0 KEY: SW_Cal_Dly Cal_Dly Act_Dly DDR PDL Configuration Register 5 Clk_Dly SW_Cal_Dly Cal_Dly Act_Dly xxh yyh xxh yyh xxh yyh xxh B c c c B c c FSB FSB B= Mandatory BIOS function A= AGP setup by BIOS P= Power management setup by BIOS o = Setup by OS or OS driver r = Hardcoded and reserved u = PCI operational user interface c = Calculated/set by AMD-762TM sys. controller internal logic F = Performance enhancement set by BIOS E = Elective BIOS function Chapter 7 Recommended BIOS Settings 249 Preliminary Information AMD-762TM System Controller Software/BIOS Design Guide 24462D--March 2002 Registers ----Bits 0x0x1x5Ch 31:24 23:16 15:8 7:0 0x0x1x60h 31:24 23:16 15:8 7:0 0x0x1x64h 31:24 23:16 15:8 7:0 0x0x1x68h 31:24 23:16 15:8 7:0 0x0x1x6Ch 31:24 23:16 15:8 7:0 KEY: Description DDR PDL Configuration Register 6 Clk_Dly SW_Cal_Dly Cal_Dly Act_Dly DDR PDL Configuration Register 7 Clk_Dly SW_Cal_Dly Cal_Dly Act_Dly DDR PDL Configuration Register 8 Clk_Dly SW_Cal_Dly Cal_Dly Act_Dly DDR PDL Configuration Register 9 Clk_Dly SW_Cal_Dly Cal_Dly Act_Dly DDR PDL Configuration Register 10 Clk_Dly SW_Cal_Dly Cal_Dly Act_Dly Initialized/ Required Value yyh xxh yyh xxh yyh xxh yyh xxh yyh xxh yyh xxh yyh xxh yyh xxh yyh xxh yyh xxh Actual Value Key c B c c c B c c c B c c c B c c c B c c fcn( ) Notes Half Period of the Sys. Clk. Delay for DQS: 100 MHz = 69h 133 MHz = 6Bh SW_Cal_Dly in # of Buffers From SW_Recal or Direct Write Half Period of the Sys. Clk. Delay for DQS: 100 MHz = 69h 133 MHz = 6Bh SW_Cal_Dly in # of Buffers From SW_Recal or Direct Write Half Period of the Sys. Clk. Delay for DQS: 100 MHz = 69h 133 MHz = 6Bh SW_Cal_Dly in # of Buffers From SW_Recal or Direct Write Half Period of the Sys. Clk. Delay for DQS: 100 MHz = 69h 133 MHz = 6Bh SW_Cal_Dly in # of Buffers From SW_Recal or Direct Write Half Period of the Sys. Clk. Delay for DQS: 100 MHz = 69h 133 MHz = 6Bh SW_Cal_Dly in # of Buffers From SW_Recal or Direct Write FSB FSB FSB FSB FSB B= Mandatory BIOS function A= AGP setup by BIOS P= Power management setup by BIOS o = Setup by OS or OS driver r = Hardcoded and reserved u = PCI operational user interface c = Calculated/set by AMD-762TM sys. controller internal logic F = Performance enhancement set by BIOS E = Elective BIOS function 250 Recommended BIOS Settings Chapter 7 Preliminary Information 24462D--March 2002 AMD-762TM System Controller Software/BIOS Design Guide Registers ----Bits 0x0x1x70h 31:24 23:16 15:8 7:0 0x0x1x74h 31:24 23:16 15:8 7:0 0x0x1x78h 31:24 23:16 15:8 7:0 0x0x1x7Ch 31:24 23:16 15:8 7:0 KEY: Description DDR PDL Config Register 11 Clk_Dly SW_Cal_Dly Cal_Dly Act_Dly DDR PDL Config Register 12 Clk_Dly SW_Cal_Dly Cal_Dly Act_Dly DDR PDL Config Register 13 Clk_Dly SW_Cal_Dly Cal_Dly Act_Dly DDR PDL Config Register 14 Clk_Dly SW_Cal_Dly Cal_Dly Act_Dly Initialized/ Required Value yyh xxh yyh xxh yyh xxh yyh xxh yyh xxh yyh xxh yyh xxh yyh xxh Actual Value Key fcn( ) Notes c B c c c B c c c B c c c B c c FSB FSB FSB FSB Half Period of the System Clock Delay for DQS: 100 MHz = 69h 133 MHz = 6Bh SW_Cal_Dly in # of Buffers From SW_Recal or Direct Write Half Period of the System Clock Delay for DQS: 100 MHz = 69h 133 MHz = 6Bh SW_Cal_Dly in # of Buffers From SW_Recal or Direct Write Half Period of the System Clock Delay for DQS: 100 MHz = 69h 133 MHz = 6Bh SW_Cal_Dly in # of Buffers From SW_Recal or Direct Write Half Period of the System Clock Delay for DQS: 100 MHz = 69h 133 MHz = 6Bh SW_Cal_Dly in # of Buffers From SW_Recal or Direct Write B= Mandatory BIOS function A= AGP setup by BIOS P= Power management setup by BIOS o = Setup by OS or OS driver r = Hardcoded and reserved u = PCI operational user interface c = Calculated/set by AMD-762TM sys. controller internal logic F = Performance enhancement set by BIOS E = Elective BIOS function Chapter 7 Recommended BIOS Settings 251 Preliminary Information AMD-762TM System Controller Software/BIOS Design Guide 24462D--March 2002 Registers ----Bits 0x0x1x8h 31:24 23:16 15:8 7:0 0x0x1x8h 31:24 23:16 15:8 7:0 0x0x1x8h 31:24 23:16 15:8 7:0 KEY: Description DDR PDL Config Register 15 Clk_Dly SW_Cal_Dly Cal_Dly Act_Dly DDR PDL Config Register 16 Clk_Dly SW_Cal_Dly Cal_Dly Act_Dly DDR PDL Config Register 17 Clk_Dly SW_Cal_Dly Cal_Dly Act_Dly Initialized/ Required Value yyh xxh yyh xxh yyh xxh yyh xxh yyh xxh yyh xxh Actual Value Key fcn( ) Notes c B c c c B c c c B c c FSB FSB FSB Half Period of the System Clock Delay for DQS: 100 MHz = 69h 133 MHz = 6Bh SW_Cal_Dly in # of Buffers From SW_Recal or Direct Write Half Period of the System Clock Delay for DQS: 100 MHz = 69h 133 MHz = 6Bh SW_Cal_Dly in # of Buffers From SW_Recal or Direct Write Half Period of the System Clock Delay for DQS: 100 MHz = 69h 133 MHz = 6Bh SW_Cal_Dly in # of Buffers From SW_Recal or Direct Write B= Mandatory BIOS function A= AGP setup by BIOS P= Power management setup by BIOS o = Setup by OS or OS driver r = Hardcoded and reserved u = PCI operational user interface c = Calculated/set by AMD-762TM sys. controller internal logic F = Performance enhancement set by BIOS E = Elective BIOS function 252 Recommended BIOS Settings Chapter 7 Preliminary Information 24462D--March 2002 AMD-762TM System Controller Software/BIOS Design Guide Registers ----Bits 0x0x1x8Ch 31:30 29:27 26:24 23:20 19:18 17:16 15:14 13:11 10:8 7:4 3:2 1:0 KEY: Description DDR DQS/MDAT Pad Config Reserved PSlewMDAT NSlewMDAT Reserved PDrvMDAT NDrvMDAT Reserved PSlewDQS NSlewDQS Reserved PDrvDQS NDrvDQS Initialized/ Required Value 00b 101b 101b 0h 11b 10b 00b 101b 101b 0h 11b 10b Actual Value Key fcn( ) Notes r B B r B B r B B r B B Weakest 00b<->11b Strongest DQS P Transistor Drv Strength Weakest 00b<->11b Strongest DQS N Transistor Drv Strength c = Calculated/set by AMD-762TM sys. controller internal logic F = Performance enhancement set by BIOS E = Elective BIOS function Slowest 000b <-> 111b Fastest MDAT Rising Edge Slew Rate Slowest 000b <-> 111b Fastest MDAT Falling Edge Slew Rate Weakest 00b<->11b Strongest MDAT P Transistor Drv Strength Weakest 00b<->11b Strongest MDAT N Transistor Drv Strength Slowest 000b <-> 111b Fastest DQS Rising Edge Slew Rate Slowest 000b <-> 111b Fastest DQS Falling Edge Slew Rate B= Mandatory BIOS function A= AGP setup by BIOS P= Power management setup by BIOS o = Setup by OS or OS driver r = Hardcoded and reserved u = PCI operational user interface Chapter 7 Recommended BIOS Settings 253 Preliminary Information AMD-762TM System Controller Software/BIOS Design Guide 24462D--March 2002 Registers ----Bits 0x0x1x90h 31:30 29:27 26:24 23:20 19:18 17:16 15:14 13:11 10:8 7:4 3:2 1:0 KEY: Description DDR CLK/CS Pad Configuration Reserved PSlewCLK NSlewCLK Reserved PDrvCLK NDrvCLK Reserved PSlewCS NSlewCS Reserved PDrvCS NDrvCS Initialized/ Required Value Actual Value Key fcn( ) Notes 00b 101b 101b 0h 11b 10b 00b 101b 101b 0h 11b 10b r B B r B B r B B r B B Weakest 00b<->11b Strongest CS P Transistor Drv Strength Weakest 00b<->11b Strongest CS N Transistor Drv Strength c = Calculated/set by AMD-762TM sys. controller internal logic F = Performance enhancement set by BIOS E = Elective BIOS function Slowest 000b <-> 111b Fastest CLK Rising Edge Slew Rate Slowest 000b <-> 111b Fastest CLK Falling Edge Slew Rate Weakest 00b<->11b Strongest CLK P Transistor Drv Strength Weakest 00b<->11b Strongest CLK N Transistor Drv Strength Slowest 000b <-> 111b Fastest CS Rising Edge Slew Rate Slowest 000b <-> 111b Fastest CS Falling Edge Slew Rate B= Mandatory BIOS function A= AGP setup by BIOS P= Power management setup by BIOS o = Setup by OS or OS driver r = Hardcoded and reserved u = PCI operational user interface 254 Recommended BIOS Settings Chapter 7 Preliminary Information 24462D--March 2002 AMD-762TM System Controller Software/BIOS Design Guide Registers ----Bits 0x0x1x94h 31:30 29:27 26:24 23:20 19:18 17:16 15:14 13:11 10:8 7:4 3:2 1:0 KEY: Description DDR CMDB/CMDA Pad Configuration Reserved PSlewCMDB NSlewCMDB Reserved PDrvCMDB NDrvCMDB Reserved PSlewCMDA NSlewCMDA Reserved PDrvCMDA NDrvCMDA Initialized/ Required Value Actual Value Key fcn( ) Notes 00b 101b 101b 0h 11b 10b 00b 101b 101b 0h 11b 10b r B B r B B r B B r B B Weakest 00b<->11b Strongest CMDA P Transistor Drv Strength Weakest 00b<->11b Strongest CMDA N Transistor Drv Strength c = Calculated/set by AMD-762TM sys. controller internal logic F = Performance enhancement set by BIOS E = Elective BIOS function Slowest 000b <-> 111b Fastest CMDB Rising Edge Slew Rate Slowest 000b <-> 111b Fastest CMDB Falling Edge Slew Rate Weakest 00b<->11b Strongest CMDB P Transistor Drv Strength Weakest 00b<->11b Strongest CMDB N Transistor Drv Strength Slowest 000b <-> 111b Fastest CMDA Rising Edge Slew Rate Slowest 000b <-> 111b Fastest CMDA Falling Edge Slew Rate B= Mandatory BIOS function A= AGP setup by BIOS P= Power management setup by BIOS o = Setup by OS or OS driver r = Hardcoded and reserved u = PCI operational user interface Chapter 7 Recommended BIOS Settings 255 Preliminary Information AMD-762TM System Controller Software/BIOS Design Guide 24462D--March 2002 Registers ----Bits 0x0x1x98h 31:30 29:27 26:24 23:20 19:18 17:16 15:14 13:11 10:8 7:4 3:2 1:0 KEY: Description DDR MAA/MAB Pad Configuration Reserved PSlewMAB NSlewMAB Reserved PDrvMAB NDrvMAB Reserved PSlewMAA NSlewMAA Reserved PDrvMAA NDrvMAA Initialized/ Required Value Actual Value Key fcn( ) Notes 00b 101b 101b 0h 11b 10b 00b 101b 101b 0h 11b 10b r B B r B B r B B r B B Weakest 00b<->11b Strongest MAA P Transistor Drv Strength Weakest 00b<->11b Strongest MAA N Transistor Drv Strength c = Calculated/set by AMD-762TM sys. controller internal logic F = Performance enhancement set by BIOS E = Elective BIOS function Slowest 000b <-> 111b Fastest MAB Rising Edge Slew Rate Slowest 000b <-> 111b Fastest MAB Falling Edge Slew Rate Weakest 00b<->11b Strongest MAB P Transistor Drv Strength Weakest 00b<->11b Strongest MAB N Transistor Drv Strength Slowest 000b <-> 111b Fastest MAA Rising Edge Slew Rate Slowest 000b <-> 111b Fastest MAA Falling Edge Slew Rate B= Mandatory BIOS function A= AGP setup by BIOS P= Power management setup by BIOS o = Setup by OS or OS driver r = Hardcoded and reserved u = PCI operational user interface 256 Recommended BIOS Settings Chapter 7 Preliminary Information 24462D--March 2002 AMD-762TM System Controller Software/BIOS Design Guide 7.2 PCI Bus 0, Device 1, Function 0 Registers Device 1 registers provide the necessary controls for the AMD-762 system controller's internal PCI-to-PCI bridge and AGP controller functions. The PCI to PCI bridge functions as a logical bridge between the Host PCI bus and the AGP interface and contains the normal PCI configuration registers for such a device. Most of these bits are read-only. Chapter 7 Recommended BIOS Settings 257 Preliminary Information AMD-762TM System Controller Software/BIOS Design Guide 24462D--March 2002 Registers ----Bits 0x1x0x00h 31:16 15:0 0x1x0x04h 31 30 29 28 27 26:25 24 23 22 21 20 19:10 9 8 7 6 5 4 3 2 1 0 0x1x0x08h 31:24 23:16 15:8 7:0 KEY: Description PCI ID Device ID Vendor ID PCI Command and Status PERR_Rcv SERR Sent Master ABRT Target ABRT Target ABRTS Signaled DEVSEL_Timing Data_PERR FastB2B UDF 66M Cap_Lst Reserved FBACK SERR, System Error Enable Step PERR VGA Palette Snoop MWINV SCYC MSTR MEM IO PCI Rev ID and Class Code Class Code Sub_Class Code Prog. I/F Revision ID Initialized/ Required Value 700Dh 1022h 0b yb 0b 0b 0b 01b 0b 0b 0b 1b 0b 00b 00h 0b yb 0b 0b 0b 0b 0b 1b 1b 1b 06h 04h 00h 00h Actual Value Key fcn( ) Notes r r r u r r r r r r r r r r u r r r r r B B B r r r r AMD-762TM system controller AMD Not supported R/W/1C, from AMD-762 system controller R/W/1C, from bus master R/W/1C, from bus master target Not supported Support 66 MHz on device 1 0 = Disable, 1 = Enable DMA enabled on APCI Memory access enable on APCI IO access Enabled on APCI Bridge device Host/PCI bridge Host/PCI bridge B= Mandatory BIOS function A= AGP setup by BIOS P= Power management setup by BIOS o = Setup by OS or OS driver r = Hardcoded and reserved u = PCI operational user interface c = Calculated/set by AMD-762TM sys. controller internal logic F = Performance enhancement set by BIOS E = Elective BIOS function 258 Recommended BIOS Settings Chapter 7 Preliminary Information 24462D--March 2002 AMD-762TM System Controller Software/BIOS Design Guide Registers ----Bits 0x1x0x0Ch 31:24 23:16 15:8 7:0 0x1x0x18h 31:24 23:16 15:8 7:0 KEY: Description AGP/PCI Header Type Reserved Header_Type Pri_Lat_Timer Reserved AGP/PCI Sub Bus Num/ Secondary Latency Timer Secon_Lat_Timer Sub_Bus_Num Secon_Bus_Num Pri_Bus_Num Initialized/ Required Value 00h 01h 40h 00h Actual Value Key fcn( ) Notes r r B r 40h 01h 01h 00h B B B r c = Calculated/set by AMD-762TM sys. controller internal logic F = Performance enhancement set by BIOS E = Elective BIOS function B= Mandatory BIOS function A= AGP setup by BIOS P= Power management setup by BIOS o = Setup by OS or OS driver r = Hardcoded and reserved u = PCI operational user interface Chapter 7 Recommended BIOS Settings 259 Preliminary Information AMD-762TM System Controller Software/BIOS Design Guide 24462D--March 2002 Registers ----Bits 0x1x0x1Ch 31 30 29 28 27 26:25 24 23 22 21 20 19:16 15:12 Description PCI Command and Status PERR_Rcv SERR_Rcv Master ABRT Target ABRT Target ABRTS Signaled DEVSEL_Timing Data_PERR FastB2B UDF 66M Cap_Lst Reserved IO_Lim[15:12] Initialized/ Required Value 0b yb yb yb 0b 01b 0b 0b 0b 1b 0b 0h xh Actual Value Key fcn( ) Notes r u u u r r r r r r r r B Not supported R/W/1C from AMD-762TM system controller R/W/1C from bus master R/W/1c from bus master target Not supported 11:8 IOLimit_R 1h r 7:4 IOBase [15:12] xh B 3:0 IOBase_R 1h r Upper 4 bits defining top address that is used by the bridge to forward I/O transactions from one interface to another. Lower 4 bits defining top address that is used by the bridge to forward I/O transactions from one interface to another. 0x1 indicates that 32 bit I/O address decoding is available Writable 4 bits that defines bottom address that is used by the bridge to forward I/O transactions from one interface to another. Lower 4 bits defining bottom address that is used by the bridge to forward I/O transactions from one interface to another. 0x1 indicates that 32 bit I/O address decoding is available. c = Calculated/set by AMD-762TM sys. controller internal logic F = Performance enhancement set by BIOS E = Elective BIOS function KEY: B= Mandatory BIOS function A= AGP setup by BIOS P= Power management setup by BIOS o = Setup by OS or OS driver r = Hardcoded and reserved u = PCI operational user interface 260 Recommended BIOS Settings Chapter 7 Preliminary Information 24462D--March 2002 AMD-762TM System Controller Software/BIOS Design Guide Registers ----Bits 0x1x0x20h Description AGP/PCI Memory Limit and Base Initialized/ Required Value Actual Value Key fcn( ) Notes 31:20 MLim[31:20] xxxh B Memory Limit Address defining top address to be used by AGP target graphics controller for control registers and buffers. The lower 20 bits are 0xFFFFF for 1-Mbyte granularity. Memory Limit Address defining lower address to be used by AGP target graphics controller for control registers and buffers. The lower 20 bits are 0xFFFFF for 1-Mbyte granularity. 19:16 Reserved 0h r 15:4 MBase[31:20] xxxh B 3:0 0x1x0x24h Reserved AGP/PCI Prefetchable Memory Limit and Base 0h r 31:20 MLim [31:20] xxxh B Prefetchable Memory Limit Address defining top address to be used by AGP target graphics controller for control registers and buffers. The lower 20 bits are 0xFFFFF for 1-Mbyte granularity. Prefetchable Memory Base Address defining lower address to be used by AGP target graphics controller for control registers and buffers. The lower 20 bits are 0xFFFFF for 1-Mbyte granularity. 19:16 0h r 15:4 MBase [31:20] xxxh B 3:0 KEY: Reserved 0h r c = Calculated/set by AMD-762TM sys. controller internal logic F = Performance enhancement set by BIOS E = Elective BIOS function B= Mandatory BIOS function A= AGP setup by BIOS P= Power management setup by BIOS o = Setup by OS or OS driver r = Hardcoded and reserved u = PCI operational user interface Chapter 7 Recommended BIOS Settings 261 Preliminary Information AMD-762TM System Controller Software/BIOS Design Guide 24462D--March 2002 Registers ----Bits 0x1x0x30h 31:24 23:16 15:8 7:0 Description AGP/PCI I/O Limit and Base Reserved IO_ Lim [23:16] Reserved IO_ Base [23:16] AGP/PCI Interrupt and Bridge Control Reserved Bridge_Fast_B2B_En Secon_Bus_ Reset Mas_Abort_Mode Reserved VGA_En ISA_En SERR_En Par_Resp_En Int_Pin Int_Line Miscellaneous Device 1 Control Reserved Int_Pin_Cntl Initialized/ Required Value 00h xxh 00h xxh Actual Value Key fcn( ) Notes r B r B This field defines the base (inclusive) of the 24bit I/O addresses passed to the AGP/PCI bus. This field defines the upper limit (inclusive) of the 24bit I/O addresses passed to the AGP/PCI bus. 0x1x0x3Ch 31:24 23 22 21 20 19 18 17 16 15:8 7:0 0x1x0x40h 31:1 0 KEY: 00h 0b 0b 0b 0b 1b 0b yb 0b xxh xxh 000b 0000000h xb r r r r r B B u r B B Enabled by 0x1x0x40[0] r B 1=Enable 0x1x0x3C[15:8] B= Mandatory BIOS function A= AGP setup by BIOS P= Power management setup by BIOS o = Setup by OS or OS driver r = Hardcoded and reserved u = PCI operational user interface c = Calculated/set by AMD-762TM sys. controller internal logic F = Performance enhancement set by BIOS E = Elective BIOS function 262 Recommended BIOS Settings Chapter 7 |
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